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US 9,177,622 B2Granted
Supply independent delayer
AssigneeMicron Technology, Inc.
InventorMarco Sforzin
Life of this patent
Estimating the term…
Abstract
Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed.
Claims15
A delay apparatus comprising:
- an input node configured to receive a signal;
- an output node configured to output a representation of the signal delayed by a delay time;
- an inverter chain coupled between the input node and the output node and comprising a plurality of inverters wherein each inverter is configured to generate a respective delay in response to a first reference voltage and a second reference voltage such that the delay time is equal to a sum of each respective delay;
- a first reference voltage generator configured to generate the first reference voltage, the first reference voltage generator comprising:
- a first current generator configured to generate a first current;
- a first transistor coupled to the first current generator, the first transistor comprising a collector node coupled to a supply voltage, VCC, and a drain node coupled to the first current generator;
- and
- a first resistance coupled between the supply voltage, VCC, and the drain node, wherein the drain node provides the first reference voltage;
- and
- a second reference voltage generator configured to generate the second reference voltage.
7 more elements
A memory device comprising:
- memory circuits;
- and
- a delayer configured to generate a delayed signal for the memory circuits, the delayer comprising:
- an inverter chain coupled between an input node, configured to receive a signal, and an output node, configured to output the delayed signal, and comprising a plurality of inverters wherein each inverter is configured to generate a respective delay in response to a first reference current and a second reference current;
- a first circuit configured to generate the first reference current;
- and
- a second circuit configured to generate the second reference current, the second circuit comprising:
- a current generator configured to generate the second reference current;
- a transistor coupled to the current generator, the transistor comprising a source node coupled to a supply voltage, VSS, and a drain node coupled to the current generator;
- and
- a resistance coupled between the supply voltage, VSS, and the drain node, wherein the drain node sources the second reference current.
8 more elements
A system comprising:
- a controller;
- and
- a memory device coupled to the controller, the memory device having a delay circuit comprising:
- an inverter chain configured to generate a delay time, the inverter chain coupled between an input node and an output node and comprising a plurality of inverters wherein each inverter is configured to generate a respective delay in response to a first reference voltage and a second reference voltage such that the delay time is equal to a sum of each respective delay wherein the delay circuit further includes a first circuit having a first current generator coupled to a reference supply voltage node, the first current generator coupled to the supply voltage node by a first resistor in parallel with a first transistor to generate the first reference voltage.
1 more element
Dependencies are inferred from the claim text.