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US 9,177,621 B2Granted
Fast bit-line pre-charge scheme
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Chang Yu, Ku-Feng Lin
Life of this patent
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Abstract
A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.
Claims20
A device comprising:
- a capacitor;
- a first voltage node;
- a first switch configured to control a connection between the first voltage node and the capacitor;
- a common charge node;
- a second switch configured to control a connection between the common charge node and the capacitor;
- a plurality of bit-lines;
- and
- a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.
5 more elements
A device comprising:
- a first voltage node and a second voltage node;
- a capacitor;
- a first switch coupled between the first voltage node and the capacitor;
- a common charge node;
- a second switch coupled between the common charge node and the capacitor;
- a third switch coupled between the second voltage node and the common charge node;
- a memory array comprising a plurality of bit-lines;
- and
- a plurality of bit-line charge switches, each coupled between the common charge node and one of the plurality of bit-lines.
6 more elements
A method comprising:
- charging a capacitor using a first voltage, wherein charges are stored on the capacitor by the step of charging;
- and
- sharing the charges on the capacitor by the capacitor and a bit-line of a memory array to pre-charge the bit-line.
Dependencies are inferred from the claim text.