Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
AssigneePS4 Luxco S.a.r.l.
InventorsShetti Shanmukheshwara Rao, Ankur Goel
Life of this patent
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Abstract
A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.
Claims19
A semiconductor memory device comprising:
- a data line extending across a memory array;
- a read circuit coupled to a first end of the data line and configured to receive data transmitted on the data line;
- a driver circuit coupled to the data line and being configured to drive the data line from a first potential to a second potential;
- and
- an assist circuit coupled to the data line at a location away from the first end of the data line, wherein the assist circuit is configured to assist the driver circuit in driving the data line from the first potential to the second potential;
- wherein the assist circuit assists the driver circuit in driving the data line from the first potential to the second potential in response to a potential of the data line dropping below a prescribed value.
A semiconductor memory device comprising:
- a data line extending across a memory array;
- a read circuit coupled to a first end of the data line and configured to receive data transmitted on the data line;
- a driver circuit coupled to the data line and being configured to drive the data line from a first potential to a second potential;
- and
- an assist circuit coupled to the data line at a location away from the first end of the data line, wherein the assist circuit is configured to assist the driver circuit in driving the data line from the first potential to the second potential;
- wherein the memory array comprises a plurality of memory banks and the location away from the first end of the data line to which the assist circuit is coupled is located within one of the plurality of memory banks.
A method comprising:
- precharging a data line associated with a memory array of a semiconductor device;
- activating a driver circuit to discharge the data line to a lower potential;
- and
- activating an assist circuit to assist the drive circuit in discharging the data line to the lower potential when the potential of the data line drops below a predetermined threshold, wherein the discharging of the data line by the drive circuit and the assist circuit occurs at least partially in parallel.
Dependencies are inferred from the claim text.