Semiconductor device having hierarchical bit line structure

A semiconductor device comprising:

• a first local bit line extending in a first direction;
• a second local bit line extending in the first direction;
• a plurality of first word lines each intersecting the first local bit line;
• a plurality of second word lines each intersecting the second local bit line;
• a plurality of first memory cells each coupled to the first bit line and an associate one of the first word lines;
• a plurality of second memory cells each coupled to the second bit line and an associate one of the second word lines;
• a sense amplifier arranged between the first and second local bit lines and including first and second nodes that are connected to the first and second local bit lines, respectively, the sense amplifier being configured to amplify a potential difference between the first and second nodes;
• a global bit line extending in the first direction along the first and second local bit lines;
• a first transistor circuit coupled to the first local bit line and the global bit line;
• and
• a second transistor circuit coupled to the second local bit line and the global bit line,
• wherein the first transistor circuit comprises a first transistor including a source-drain path connected between the first local bit line and the global bit line and a gate supplied with a first control signal, and the second transistor circuit comprises a second transistor including a source-drain path connected between the second local bit line and the global bit line and a gate supplied with a second control signal, and
• wherein the first control signal takes an active level to turn the first transistor ON in response to one of the first memory cells being selected, and the second control signal takes an active level to turn the second transistor ON in response to one of the second memory cells being selected.

A semiconductor device comprising:

• a global bit line extending in a first direction;
• a global sense amplifier coupled to the global bit line to amplify a potential on the global bit line;
• a first local bit line extending in the first direction in substantially parallel to the global bit line, the first local bit line including first and second end portions and a first intermediate portion therebetween;
• a plurality of first memory cells each coupled to the first intermediate portion of the first local bit line;
• a second local bit line extending in the first direction in substantially parallel to the global bit line, the second local bit line including third and fourth end portions and a second intermediate portion therebetween;
• a plurality of second memory cells each coupled to the second intermediate portion of the second local bit line;
• a first local sense amplifier between the first end portion of the first local bit line and the third end portion of the second local bit line, the first local sense amplifier being configured to amplify a potential difference between the first and second local bit lines;
• a first transistor coupled between the first end portion of the first local bit line and the global bit line;
• a second transistor coupled between the second end portion of the first local bit line and the global bit line;
• a third transistor coupled between the third end portion of the second local bit line and the global bit line;
• and
• a fourth transistor coupled between the fourth end portion of the second local bit line and the global bit line.

A semiconductor device comprising:

• a first local bit line extending in a first direction;
• a second local bit line extending in the first direction;
• a plurality of first word lines each intersecting the first local bit line;
• a plurality of second word lines each intersecting the second local bit line;
• a plurality of first memory cells each coupled to the first bit line and an associate one of the first word lines;
• a plurality of second memory cells each coupled to the second bit line and an associate one of the second word lines;
• a sense amplifier arranged between the first and second local bit lines and including first and second nodes that are connected to the first and second local bit lines, respectively, the sense amplifier being configured to amplify a potential difference between the first and second nodes;
• a global bit line extending in the first direction along the first and second local bit lines;
• a first transistor circuit coupled to the first local bit line and the global bit line;
• and
• a second transistor circuit coupled to the second local bit line and the global bit line,
• wherein the first transistor circuit comprises:
• a first transistor including a source-drain path connected between the first local bit line and the global bit line and a gate supplied with a first control signal;
• a second transistor including a source-drain path and a gate supplied with a second control signal;
• and
• a third transistor including a source-drain path and a gate connected to the first local bit line, the source-drain paths of the second and third transistors being connected in series between the global bit line and a reference potential line, wherein the first transistor circuit comprises:
• a fourth transistor including a source-drain path connected between the second local bit line and the global bit line and a gate supplied with a third control signal,
• a fifth transistor including a source-drain path and a gate supplied with a fourth control signal, and
• a sixth transistor including a source-drain path and a gate connected to the second local bit line, the source-drain paths of the fifth and sixth transistors being connected in series between the global bit line and the reference potential line.