Supply power dependent controllable write throughput for memory applications
AssigneeCypress Semiconductor Corporation
InventorEvrim Binboga
Life of this patent
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Abstract
Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput.
Claims22
A method of managing throughput in a memory device, comprising:
- monitoring a power supply level;
- determining an appropriate memory write throughput based on a number of cells to which the memory device can write at a time at the monitored power supply level;
- generating a control signal based on the determined memory write throughput, wherein the control signal is configured to cause a driver circuit to activate a portion of a memory array consistent with said determined memory write throughput.
A memory device, comprising:
- a memory array comprising a plurality of memory cells;
- a controller configured to:
- monitor a power supply level,
- determine an appropriate memory write throughput based on a number of cells to which the memory device can write at a time at the monitored power supply level, and
- generate a control signal based on the determined memory write throughput;
- and
- a driver circuit configured to selectively drive portions of the memory array based on a received control signal.
Dependencies are inferred from the claim text.