Smart bridge for memory core

An apparatus comprising:

• a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory further includes circuitry associated with operation of the multiple memory cells;
• a second semiconductor die including a memory device interface and a memory controller interface, wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface;
• and
• a third semiconductor die that includes a memory controller of the 3D memory, wherein the third semiconductor die includes a host interface, a memory interface, a processor, and an error correction coding (ECC) engine, wherein the host interface is configured to enable communication with a host device, and wherein the memory interface is coupled to the memory controller interface of the second semiconductor die,
• wherein the memory device interface and the memory controller interface of the second semiconductor die are configured to enable communication of data and control information between the memory controller and the 3D memory.