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US 9,177,610 B2Granted
Smart bridge for memory core
AssigneeSanDisk Technologies LLC
InventorsManuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
Life of this patent
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Abstract
An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.
Claims12
An apparatus comprising:
- a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells;
- and
- a second semiconductor die including:
- a memory device interface;
- a memory controller interface;
- and
- periphery circuitry associated with the 3D memory;
- wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface, and wherein the memory controller interface is configured to be coupled to a memory interface of a memory controller die to enable communication of data and control information between the memory controller die and the 3D memory via the memory device interface and the memory controller interface of the second semiconductor die.
5 more elements
A method comprising:
- receiving data at a second semiconductor die for storage at a three-dimensional (3D) memory at a first semiconductor die, wherein the second semiconductor die includes a memory device interface, a memory controller interface, and periphery circuitry for the 3D memory;
- and
- sending a control signal from the second semiconductor die to the 3D memory at the first semiconductor die,
- wherein the 3D memory includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate and wherein the 3D memory includes circuitry associated with operation of the multiple memory cells,
- wherein the second semiconductor die is coupled to the first semiconductor die via the memory device interface, and
- wherein the memory controller interface is configured to be coupled to a memory interface of a memory controller die to enable communication between the memory controller die and the 3D memory via the memory device interface and the memory controller interface of the second semiconductor die.
3 more elements
Dependencies are inferred from the claim text.