Bi-directional scan driver and display device using the same

A display device comprising:

• a display unit including a plurality of pixels;
• a scan driver for transmitting at least two different types of scan signals to the plurality of pixels;
• a data driver for transmitting a data signal to the plurality of pixels;
• a light emission control driver for transmitting a light emission control signal to the plurality of pixels;
• and
• a signal controller for generating and transmitting a plurality of control signals for controlling the scan driver, the data driver, and the light emission control driver,
• wherein the scan driver comprises a plurality of sequence drivers, each of the sequence drivers comprising a plurality of shift registers for generating the at least two different types of scan signals, and
• wherein one of the scan signals includes an initialization signal-generated in one of the shift registers that is transmitted as an input signal of a next one of the shift registers and as an input signal of a pixel from among the plurality of pixels coupled to the one of the shift registers, and the one of the scan signals including the initialization signal is concurrently transmitted to the shift register of one of the sequence drivers of a previous stage or a next stage adjacent to the one of the sequence drivers including the one of the shift registers as the input signal according to a driving direction of the scan driver, wherein
• each of the plurality of sequence drivers of a stage among a plurality of sequence drivers comprises:
• a first shift register for receiving a forward direction start signal and the scan signal generated in the shift register of the sequence driver of the previous stage adjacent to the sequence driver of a corresponding stage, or the scan signal generated in the shift register of the sequence driver of the next stage adjacent to the sequence driver of the corresponding stage, and a backward direction start signal as a first input signal in synchronization with a first clock signal, and for outputting one of a second clock signal and a first power source voltage as a first scan signal respectively corresponding to the first input signal and a first initialization signal;
• and
• a second shift register for receiving the first scan signal as a second input signal in synchronization with the second clock signal and for outputting one of the first clock signal and the first power source voltage as a second scan signal respectively corresponding to the second input signal and a second initialization signal, wherein the first shift register comprises:
• a first transistor configured to turn on according to the forward direction driving control signal and for transmitting the forward direction start signal and the scan signal generated in the shift register of the sequence driver of the previous stage adjacent to the sequence driver of the corresponding stage as the first input signal;
• a second transistor configured to turn on according to the backward direction driving control signal and for transmitting the scan signal generated in the shift register of the sequence driver of the next stage adjacent to the sequence driver of the corresponding stage and the backward direction start signal as the first input signal;
• a third transistor configured to turn on according to the first clock signal and for transmitting the first input signal from the first transistor or the second transistor;
• a fourth transistor for receiving the first input signal from the first transistor or the second transistor, and configured to turn on according to a voltage level of the input signal, thereby transmitting the first power source voltage;
• a fifth transistor configured to turn on according to the second power source voltage transmitted the fifth transistor according to the first initialization signal, and for transmitting the first power source voltage;
• a sixth transistor configured to turn on according to the first initialization signal and for transmitting the second power source voltage to a first node coupled to a gate electrode of the fifth transistor;
• a seventh transistor configured to turn on according to the voltage level of the input signal transmitted through the third transistor, and for outputting the second clock signal as the first scan signal;
• and
• an eighth transistor configured to turn on according to the second power source voltage transmitted to the first node, and for outputting the first power source voltage as the first scan signal.