Timing closure using transistor sizing in standard cells

A method comprising:

• creating a standard cell that includes a first set of layout properties and a second set of layout properties of a transistor included in a timing path in the standard cell, wherein the second set of layout properties is stored into a resize layer entry of annotated cell layout data associated with the standard cell;
• performing a first static timing analysis of an integrated circuit design using a first set of timing values corresponding to the first set of layout properties of the transistor included in the standard cell utilized by the integrated circuit design;
• selecting a second set of timing values in response to a timing violation from the first static timing analysis, wherein the second set of timing values correspond to the second set of layout properties of the transistor included in the standard cell;
• performing a second static timing analysis using the second set of timing values;
• and
• generating mask layer data that includes the second set of layout properties in response to a determination that the second static timing analysis resolves the timing violation, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit design.

A computer program product stored in a computer readable storage medium, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising:

• creating a standard cell that includes a first set of layout properties and a second set of layout properties of a transistor included in a timing path in the standard cell, wherein the second set of layout properties is stored into a resize layer entry of annotated cell layout data associated with the standard cell;
• performing a first static timing analysis of an integrated circuit design using a first set of timing values corresponding to the first set of layout properties of the transistor included in the standard cell utilized by the integrated circuit design;
• selecting a second set of timing values in response to a timing violation from the first static timing analysis, wherein the second set of timing values correspond to the second set of layout properties of the transistor included in the standard cell;
• performing a second static timing analysis using the second set of timing values;
• and
• generating mask layer data that includes the second set of layout properties in response to a determination that the second static timing analysis resolves the timing violation, wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding to the integrated circuit design.