Routing interconnect of integrated circuit designs with varying grid densities
AssigneeCadence Design Systems, Inc.
InventorsLimin He, So-Zen Yao, Wenyong Deng, Jing Chen, Liang-Jih Chao
Life of this patent
Estimating the term…
Abstract
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Claims12
A method of routing an integrated circuit (IC) design, comprising:
- accessing the IC design including a plurality of objects on one or more layers;
- forming a plurality of levels, wherein the plurality of levels includes
- a first level representing the IC design at a first grid density,
- a second level representing the IC design at a second grid density finer than at least the first grid density, and
- a third level representing the IC design at a third grid density finer than at least the first grid density and the second grid density;
- based at least partly on the IC design, populating each level of the plurality of levels with the plurality of objects;
- interconnecting the plurality of objects at one or more of the first level, the second level, and the third level;
- and
- initiating generation of an integrated circuit from the IC design based on the accessing, forming, populating, and interconnecting;
- wherein one or more of the accessing, forming, populating, and interconnecting is performed using a computer.
A method of routing an integrated circuit (IC) design, comprising:
- forming a first plurality of nodes for positioning objects of the IC design in a first layer using a computer, wherein
- at least two nodes of the first plurality of nodes are spaced apart by a first interval;
- forming a second plurality of nodes for positioning objects of the IC design in a second layer using a computer, wherein
- at least two nodes of the second plurality of nodes are spaced apart by the first interval, and
- at least two nodes of the second plurality of nodes are spaced apart by one or more intervals greater than the first interval;
- and
- generating an IC from the IC design using the first plurality of nodes and the second plurality of nodes.
A method of routing an integrated circuit (IC) design, comprising:
- forming a first plurality of nodes for positioning objects of the IC design in a first layer using a computer, wherein
- at least two nodes of the first plurality of nodes are spaced apart by a first interval;
- forming a second plurality of nodes for positioning objects of the IC design in a second layer using a computer, wherein
- at least two nodes of the second plurality of nodes are spaced apart by the first interval, and
- at least two nodes of the second plurality of nodes are spaced apart by one or more intervals less than the first interval;
- and
- initiating generation of an IC from the IC design using the first plurality of nodes and the second plurality of nodes.
Dependencies are inferred from the claim text.