Method for arranging and wiring reconfigurable semiconductor device, program therefor, and arranging and wiring apparatus
AssigneeTaiyo Yuden Co., Ltd.
InventorMasayuki Satou
Life of this patent
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Abstract
An arrangement and wiring method of a reconfigurable semiconductor device, including: generating a net list based on a circuit description in which a circuit configuration is described; extracting a sequential circuit data set which is to be scanned from the net list; generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned; and generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list.
Claims5
An arrangement and wiring method of a reconfigurable semiconductor device, characterized by comprising:
- generating a net list based on a circuit description in which a circuit configuration is described;
- extracting a sequential circuit data set which is to be scanned from the net list;
- generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned;
- and
- generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list;
- wherein the reconfigurable device includes the plurality of memory cell units configuring arrays and are connected to each other, and the memory cell units operate as a logic element when truth value table data is written in configured so as to output a logic calculation of an input value specified by a plurality of addresses to a data line, and/or operate as a connection element when truth value table data is written in configured so as to output an input value specified by a certain address to a data line connected to an address of another memory cell unit, and
- wherein a memory cell unit to which the first truth value table data set is allotted is simulated with an execution in synchronization with a clock, and/or the plurality of the second truth value table data sets are simulated with an execution in non-synchronization with the clock, and whether the semiconductor device realizes a certain operation speed is evaluated.
An arrangement and wiring apparatus which performs arrangement and wiring of a reconfigurable semiconductor device, characterized by comprising a processor, wherein the processor:
- generates a net list based on a circuit description in which a circuit configuration is described;
- extracts a sequential circuit data set which is to be scanned from the net list;
- generates a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned;
- and
- generates a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list;
- and
- wherein the reconfigurable semiconductor device includes the plurality of memory cell units configuring arrays, and the memory cell units operate as a logic element when truth value table data is written in configured so as to output a logic calculation of an input value specified by a plurality of addresses to a data line, and/or operate as a connection element when truth value table data is written in configured so as to output an input value specified by a certain address to a data line connected to an address of another memory cell unit, and
- wherein the processor is configured so as to simulate an execution in synchronization with a clock for a memory cell unit to which the first truth value table data set is allotted, and/or simulate an execution in non-synchronization with the clock for the plurality of the second truth value table data sets, and evaluate whether the semiconductor device realizes a certain operation speed.
A non-transitory storage medium which stores a program to arrange and wire a reconfigurable semiconductor device, characterized by making a processor execute processing of:
- generating a net list based on a circuit description in which a circuit configuration is described;
- extracting a sequential circuit data set which is to be scanned from the net list;
- generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned;
- and
- generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list;
- and wherein the reconfigurable semiconductor device includes the plurality of memory cell units configuring arrays, and the memory cell units operate as a logic element when truth value table data is written in configured so as to output a logic calculation of an input value specified by a plurality of addresses to a data line, and/or operate as a connection element when truth value table data is written in configured so as to output an input value specified by a certain address to a data line connected to an address of another memory cell unit, and
- wherein the program makes the processor execute processing of simulating an execution in synchronization with a clock for a memory cell unit to which the first truth value table data set is allotted, and/or simulating an execution in non-synchronization with the clock for the plurality of the second truth value table data sets, and evaluating whether the semiconductor device realizes a certain operation speed.
Dependencies are inferred from the claim text.