US 9,177,091 B2Granted

Row formation during datapath placement in circuit design

AssigneeOracle International Corporation

InventorsWonjoon Choi, Akshay Sharma, Huy Tran Ba Vo, Guo Yu

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Abstract

Implementations of the present disclosure involve methods and systems for component placement in a datapath block of a microelectronic circuit design. In particular, implementations provide for collecting groups of common components in the datapath block that form a row or partial row. A preliminary layout of the datapath block is performed with the component set rows and any other components of the datapath block design. Common components are then collected into groups or sets to form additional rows within the datapath layout, with at least some consideration to the wire lengths between components in the rows. By collecting common components into rows with consideration to the wire lengths between interconnected components, the timing performance of the datapath block may be improved.

Claims17

Dependent claims

A method for design of a microelectronic circuit, the method comprising:

obtaining, utilizing a processor, a netlist describing a functional block of a microelectronic circuit from a computer-readable medium, the netlist comprising a listing of a plurality of components of the functional block and at least one connection between a pair of components of the plurality of components;
identifying at least one set of associated sequential components of the functional block from the plurality of components of the netlist;
identifying at least one set of associated combinational components of the functional block from the plurality of components of the netlist;
assigning a coordinate value to each of the of the least one set of associated sequential components, the least one set of associated combinational components and a plurality of remaining components from the plurality of components of the netlist, the coordinate value indicative of a position in the footprint of the functional block relative to a fixed reference point;
assigning a unique identifier to each of the at least one set of associated sequential components, the least one set of associated combinational components and a plurality of remaining components from the plurality of components of the netlist;
creating a hypergraph containing the unique identifiers, the hypergraph indicative of the at least one connection between the pair of components of the plurality of components;
organizing the plurality of components of the functional block into a plurality of rows based at least on the hypergraph within a footprint of the functional block;
and
utilizing the organized plurality of components to generate the functional block of the microelectronic circuit.

6 more elements

A design tool for the design of a microelectronic circuit, the design tool comprising:

a computer-readable medium for storing a netlist, the netlist comprising a listing of a plurality of components of a functional block of a microelectronic circuit and a plurality of connections between the plurality of components;
a processor configured to obtain one or more executable instructions from the computer-readable medium, wherein the processor executes the one or more instructions to perform the operations of:
obtaining the netlist from the computer-readable medium;
identifying at least one set of storage components of the functional block from the plurality of components of the netlist;
identifying at least one set of associated combinational components of the functional block from the plurality of components of the netlist
assigning a coordinate value to each of the at least one set of storage components, the least one set of associated combinational components and a plurality of remaining components from the plurality of components of the netlist, the coordinate value indicative of a vertical position in the footprint of the functional block relative to a fixed reference point;
assigning a unique identifier to each of the at least one set of storage components, the least one set of associated combinational components and a plurality of remaining components from the plurality of components of the netlist;
modifying the netlist into a hypergraph, the hypergraph comprising a plurality of entries associated with the plurality of connections utilizing the unique identifiers, wherein at least one entry comprises at least one pair of unique identifiers indicating a connection between the pair of unique identifiers;
and
locating the plurality of components of the functional block into a plurality of rows based at least on the plurality of connections in the hypergraph, the locating configured to place the components associated with the at least one pair of unique identifiers in adjacent rows.

7 more elements

A non-transitory computer readable medium encoded with instructions for designing a portion of a microelectronic circuit, the instructions executable by a processor, comprising

receiving a netlist describing the circuit portion, the netlist comprising a listing of a plurality of components of the circuit portion and at least one connection between a pair of components of the plurality of components;
assigning a coordinate value to each of the of the least one set of associated sequential components, the least one set of associated combinational components and a plurality of remaining components from the plurality of components of the netlist, the coordinate value indicative of a vertical position in the footprint of the circuit portion relative to a fixed reference point;
assigning a unique identifier to each of at least one set of associated sequential components of the circuit portion from the plurality of components of the netlist, at least one set of associated combinational components of the circuit portion from the plurality of components of the netlist and a plurality of remaining components from the plurality of components of the netlist;
creating a hypergraph containing the unique identifiers, the hypergraph indicative of the at least one connection between the pair of components of the plurality of components;
organizing the plurality of components of the circuit portion into a plurality of rows based at least on the hypergraph within a footprint of the circuit portion;
and
generating the functional block of the microelectronic circuit from the organized plurality of components.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/173,618Filed 5 Feb 2014
Published: US 2015/0220673 A16 Aug 2015
Granted: 3 Nov 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 2119/12
Details relating to the type or aim of the analysis or the optimisation: timing analysis or timing optimisation
G06F
Computing and data processing