In-hierarchy circuit analysis and modification for circuit instances
AssigneeAtoptech, Inc.
InventorPing-San Tzeng
Life of this patent
Estimating the term…
Abstract
Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.
Claims21
A method comprising:
- within a top level design process performed using one or more computer processors:
- accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data, the hierarchical circuit design being used to produce a chip;
- performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved;
- and
- in the event that timing closure is not achieved, determining an optimization move on the selected portion of the hierarchical circuit data;
- wherein
- the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data;
- and
- the hierarchical circuit data is not exported or imported between the performing of the timing analysis and the determining of the optimization move.
A system comprising:
- one or more processors configured to:
- within a top level design process:
- access hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data, the hierarchical circuit design being used to produce a chip;
- perform timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved;
- and
- in the event that timing closure is not achieved, determine level design process, an optimization move on the selected portion of the hierarchical circuit data;
- wherein
- the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data;
- and
- the hierarchical circuit data is not exported or imported between the performing of the timing analysis and the determining of the optimization move;
- and
- one or more memories coupled to the one or more computer processors, configured to provide the one or more processors with instructions.
A computer program product for modifying a hierarchical circuit design, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
- within a top level design process:
- accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data, the hierarchical circuit design being used to produce a chip;
- performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved;
- and
- in the event that timing closure is not achieved, determining a set of one or more fixes on at least a part of the selected portion of the hierarchical circuit data;
- wherein
- the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data;
- and
- the hierarchical circuit data is not exported or imported between the performing of the timing analysis and the determining of the optimization move.
Dependencies are inferred from the claim text.