Methods and apparatus for generating short length patterns that induce inter-symbol interference
AssigneeAltera Corporation
InventorsMasashi Shimanouchi, Peng Li, Daniel Tun Lai Chow
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Abstract
One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.
Claims15
A method of measuring a performance of a communication link that comprises a transmitter circuit, a receiver circuit, and a communication channel therebetween, the method comprising:
- generating, by a pattern generator circuit, an inter-symbol interference inducing short pattern comprising:
- a binary clock sequence comprising a plurality of bits of alternating values;
- a first inter-symbol interference inducing binary sequence to follow the binary clock sequence in order within the inter-symbol interference inducing short pattern, wherein the first inter-symbol interference inducing binary sequence comprises repeating a first series of consecutive identical bits of a first value followed in order by one bit of a second value a plurality of times, wherein the first and second values are inverses of each other;
- and
- a second inter-symbol interference inducing binary sequence that follows the complement of the binary clock sequence in order within the inter-symbol interference inducing short pattern, wherein the second inter-symbol interference inducing binary sequence comprises repeating a second series of consecutive identical bits of the second value followed in order by one bit of the first value a plurality of times;
- transmitting, by the transmitter circuit, the inter-symbol interference inducing short pattern to the communication channel;
- receiving, by the receiver circuit, the inter-symbol interference inducing short pattern from the communication channel;
- and
- measuring the performance of the communication link to obtain measured performance data.
A transmitter circuit comprising:
- a serializer;
- a transmitter equalizer;
- a driver that outputs a data signal to a communication link;
- and
- a pattern generator circuit for generating an inter-symbol interference inducing short pattern that is provided to the serializer for testing the communication link, the pattern generator circuit comprising circuitry that generates
- a binary clock sequence comprising bits of alternating values, wherein the binary clock sequence has a clock length in bits that is greater than or equal to a channel settling time divided by one bit duration, and wherein the clock length is at least seven and less than one thousand bits,
- a first inter-symbol interference inducing binary sequence following the binary clock sequence in order within the inter-symbol interference inducing short pattern, and
- a second inter-symbol interference inducing binary sequence following the first inter-symbol interference inducing binary sequence in order within the inter-symbol interference inducing short pattern.
Dependencies are inferred from the claim text.