Coherence switch for I/O traffic

An apparatus comprising:

• a coherence switch;
• a processor complex comprising one or more processors;
• a memory controller coupled to the processor complex and to the coherence switch;
• and
• a plurality of I/O devices;
• wherein the coherence switch is configured to:
• maintain a working copy of a configuration register and a shadow copy of the configuration register, wherein the shadow copy is a software-writeable copy of the working copy of the configuration register, wherein each copy stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via a coherent path or via a non-coherent path;
• receive a plurality of transactions from the plurality of I/O devices;
• select either a coherent path or a non-coherent path for routing a received transaction based at least in part on a value stored in the shadow copy of the configuration register, wherein the indicator specifies if a received transaction is a coherent transaction or a non-coherent transaction, wherein a non-coherent transaction is a transaction for which a coherency check is not performed, wherein the coherent path passes through the processor complex to a first port of the memory controller, and wherein the non-coherent path bypasses the processor complex and passes through a second port of the memory controller;
• and
• responsive to detecting a change to the shadow copy of the configuration register:
• stop accepting new transactions from the plurality of I/O devices;
• and
• responsive to determining all outstanding transactions have been routed:
• update the working copy of the configuration register to match the shadow copy of the configuration register;
• and
• accept new transactions from the plurality of I/O devices.

A method comprising:

• receiving a first transaction and a second transaction at a coherence switch, wherein a first identifier accompanies the first transaction, and wherein a second identifier accompanies the second transaction;
• accessing a first routing indicator in a configuration register using the first identifier, and accessing a second routing indicator in the configuration register using the second identifier, wherein the configuration register is configured to store an indicator which specifies whether a received transaction should be routed to memory via a first path or a second path, wherein a non-coherent transaction is a transaction for which a coherency check is not performed;
• routing the first transaction on a first path responsive to the first routing indicator having a first value, wherein the first path passes through a processor complex to a first port of a memory controller;
• routing the second transaction on a second path responsive to the second routing indicator having a second value, wherein the second value is different than the first value, and wherein the second path is coupled to a second port of the memory controller without passing through the processor complex;
• maintaining two copies of a configuration register, wherein a first copy is a software-writeable copy of the configuration register and a second copy is a working CODY of the configuration register, wherein each coin stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via the first path or via the second path;
• responsive to detecting a change to the software-writeable copy of the configuration register:
• stop accepting new transactions from the plurality of I/O devices;
• and
• responsive to determining all outstanding transactions have been routed:
• updating the working copy of the configuration register to match the software-writeable copy of the configuration register;
• and
• accepting new transactions from the plurality of I/O devices.

A system comprising:

• a processor complex comprising one or more processors;
• a coherence switch coupled to the processor complex;
• a multiplexer coupled to the coherence switch;
• a plurality of I/O devices coupled to the multiplexer;
• a memory controller comprising a plurality of ports, wherein the memory controller is coupled to the processor complex and to the coherence switch;
• and
• a memory coupled to the memory controller;
• wherein the coherence switch is configured to:
• maintain a working copy of a configuration register and a shadow copy of the configuration register, wherein the shadow copy is a software-writeable copy of the working copy of the configuration register, wherein each copy stores an indicator for each transaction identifier that specifies whether a corresponding transaction should be routed to memory via a coherent path or via a non-coherent path;
• receive a plurality of transactions from the plurality of I/O devices via the multiplexer;
• for each transaction, determine if the transaction is a coherent or non-coherent transaction;
• responsive to determining a received transaction is a coherent transaction, route the received transaction directly to the processor complex;
• responsive to determining a received transaction is a non-coherent transaction, route the received transaction directly to the memory controller wherein a non-coherent transaction is a transaction for which a coherency check is not performed;
• responsive to detecting a change to the shadow copy of the configuration register:
• stop accepting new transactions from the plurality of I/O devices;
• and
• responsive to determining all outstanding transactions have been routed:
• update the working copy of the configuration register to match the shadow copy of the configuration register;
• and
• accept new transactions from the plurality of I/O devices.