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US 9,176,908 B2Granted
Time multiplexing at different rates to access different memory types
AssigneeRambus Inc.
InventorIan Shaeffer
Life of this patent
Estimating the term…
Abstract
A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.
Claims17
A memory controller, comprising:
- clock circuitry configured to provide clock signals having different clock rates for different types of memory devices;
- and
- an interface circuit configured to time division multiplex data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices, the interface circuit also configured to provide first write data at a first one of the clock rates for write operations directed to a first type of memory device of the different types of memory devices, wherein the first type of memory device is configured to transmit and receive over the shared signal bus at the first clock rate and to provide second write data at the first clock rate for write operations directed to a second type of memory device of the different types of memory devices, wherein the second type of memory device is configured to transmit and receive over the shared signal bus at a second one of the clock rates that is slower than the first clock rate, and a portion of the second write data comprises dummy data.
A memory controller, comprising:
- clock circuitry configured to provide clock signals having different clock rates for different types of memory devices;
- and
- an interface circuit configured to time division multiplex data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices;
- the clock signals comprising a first clock signal, a second clock signal, and at least one other clock signal;
- the first clock signal to operate at a first native clock rate associated with write operations for a first one of the memory device types;
- the second clock signal to operate at a second native clock rate associated with read operations for the first one of the memory device types;
- and
- the at least one other clock signal to operate at a third native clock rate associated with read and write operations for a second one of the memory device types.
5 more elements
A memory control apparatus, comprising:
- means for providing clock signals having different clock rates for different types of memory devices;
- and
- means for time division multiplexing data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices;
- means for providing first write data at a first one of the clock rates for write operations directed to a first type of memory device of the different types of memory devices, wherein the first type of memory device is configured to transmit and receive over the shared signal bus at the first clock rate, and
- means for providing second write data at the first clock rate for write operations directed to a second type of memory device of the different types of memory devices, wherein the second type of memory device is configured to transmit and receive over the shared signal bus at a second one of the clock rates that is slower than the first clock rate, and a portion of the second write data comprises dummy data.
2 more elements
Dependencies are inferred from the claim text.