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US 9,176,906 B2Granted
Memory controller and memory system including the same
AssigneeSK hynix Inc.
InventorsYong Kee Kwon, Hyung Dong Lee, Young Suk Moon, Hyung Gyun Yang
Life of this patent
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Abstract
A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value.
Claims18
A memory controller comprising:
- an address mapping unit configured to receive a physical address and generate a pre-address signal;
- an access control unit configured to generate an address signal from the pre-address signal, and delay the generation of the address signal by a predetermined time when pre-address signals which have same logic bits are consecutively and repetitively inputted by a number exceeding a critical value;
- and
- an arbiter configured to receive the address signal and provide the address signal to a memory unit.
1 more element
A memory system comprising:
- a memory unit comprising a plurality of memory banks;
- and
- a memory controller configured to access the memory unit,
- wherein the memory controller comprises:
- an address mapping unit configured to receive a physical address and generate a pre-address signal;
- an access control unit configured to generate an address signal from the pre-address signal, and delay the generation of the address signal by a predetermined time when pre-address signals which have same logic bits are consecutively and repetitively inputted by a number exceeding a critical value;
- and
- an arbiter configured to provide the address signal to the memory unit.
5 more elements
Dependencies are inferred from the claim text.