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US 9,176,895 B2Granted
Increased error correction for cache memories through adaptive replacement policies
AssigneeIntel Corporation
InventorsXavier Vera, Javier Carretero Casado, Enric Herrero Abellanas, Daniel Sanchez, Nicholas Axelos, Tanausu Ramirez
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Abstract
A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.
Claims17
A processor comprising:
- a core data cache;
- cache control logic to receive:
- a hit/miss from the core data cache;
- a read/write signal from a load store unit;
- and
- an eviction policy signal indicative of a detectable unrecoverable error failure in time (DUE FIT) rate of the core data cache, the eviction policy signal including one of an aggressive policy value, an intermediate policy value, and a relaxed policy value;
- and age modification logic to:
- modify an age attribute of a modified cache line based on the read/write signal and the eviction policy signal, wherein the age modification logic is to increase the age attribute of modified lines in a way responsive to assertion of the aggressive policy value.
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A method, comprising:
- obtaining detectable unrecoverable error failure in time (DUE FIT) data indicative of a DUE FIT rate;
- comparing the DUE FIT rate to a first threshold;
- and
- responsive to the DUE FIT rate exceeding the first threshold, evicting modified lines stored in a cache memory of a processor preferentially in response to read and write cache miss events, evicting the modified cache lines preferentially in response to cache write miss events responsive to the DUE FIT rate not exceeding the first threshold and exceeding a second threshold, and evicting based on a recency policy in response to cache write miss events when the DUE FIT rate does not exceed the second threshold.
1 more element
A computer system, comprising:
- a processor comprising:
- a core data cache;
- cache control logic to receive:
- a hit/miss from the core data cache;
- a read/write signal from a load store unit;
- and
- an eviction policy signal indicative of a detectable unrecoverable error failure in time (DUE FIT) rate of the core data cache;
- and
- age modification logic to:
- modify an age attribute of a modified cache line based on the read/write signal and the eviction policy signal, to cause the modified cache line to be preferentially evicted in response to a cache miss event when the DUE FIT rate exceeds a first threshold, cause the modified cache line to be preferentially evicted in response to a cache write miss event when the DUE FIT rate is less than the first threshold and exceeds a second threshold, and not modify the age attribute of the modified cache line in response to a cache write miss event when the DUE FIT rate does not exceed the second threshold.
7 more elements
Dependencies are inferred from the claim text.