Combined cache inject and lock operation
AssigneeInternational Business Machines Corporation
InventorsJamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt, Robert A. Shearer, III
Life of this patent
Estimating the term…
Abstract
A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
Claims24
A method for storing data in a network on a chip (NOC) processing unit, the method comprising:
- in a first node that includes an integrated processor block including an execution unit and a cache memory coupled to the execution unit, maintaining, for each cache line among a plurality of cache lines stored in the cache memory, each of a software lock flag and a cache inject lock flag associated with said each cache line, wherein the first node is among a plurality of nodes coupled to one another via an on-chip network;
- in response to detecting communication of a respective cache line from an input/output (I/O) device to a first memory coupled to the on-chip network, determining whether a maximum number of cache lines in the cache memory are cache inject locked by accessing a cache lock counter associated with the cache memory;
- in response to determining that the maximum number of cache lines are not cache inject locked, performing a cache inject and lock operation by injecting the respective cache line in the cache memory concurrently with communication of the respective cache line to the first memory and automatically locking the respective cache line, wherein locking the respective cache line includes setting the cache inject lock flag for the respective cache line and incrementing the cache lock counter, and wherein setting the cache inject lock flag locks the respective cache line from being evicted from the cache memory.
A method for storing data in a processing unit including an execution unit and a cache memory coupled to the execution unit, the cache memory configured to store a plurality of cache lines, the method comprising:
- maintaining, for each cache line stored in the cache memory, a software lock flag and a cache inject lock flag associated with a cache line;
- in response to detecting communication of a respective cache line from an input/output (I/O) device to a first memory coupled to the processing unit, determining whether to inject and lock the respective cache line in the cache memory;
- and in response to determining to inject and lock the respective cache line in the cache memory, performing a cache inject and lock operation using cache injection logic coupled to the cache memory to inject the respective cache line in the cache memory concurrently with communication of the respective cache line to the first memory and automatically lock the respective cache line, wherein locking the respective cache line locks the respective cache line from being evicted from the cache memory.
A circuit arrangement comprising:
- a processing unit;
- a cache memory coupled to the processing unit and configured to store a plurality of cache lines, wherein the cache memory is configured to maintain, for each cache line stored in the cache memory, a software lock indicator and a cache inject lock indicator associated with a cache line;
- and
- cache injection logic coupled to the cache memory, the cache injection logic configured to, in response to detection of a communication of a respective cache line from an input/output (I/O) device to a first memory coupled to the processing unit, determine whether to inject and lock the respective cache line in the cache memory, wherein the cache injection logic is further configured to perform a cache inject and lock operation to inject the respective cache line in the cache memory concurrently with communication of the respective cache line to the first memory and automatically lock the respective cache line in response to determining to inject and lock the respective cache line in the cache memory, wherein locking the respective cache line locks the respective cache line from being evicted from the cache memory.
Dependencies are inferred from the claim text.