Bus transaction monitoring and debugging system using FPGA

A bus transaction monitoring and debugging system, the system comprising:

• a first FPGA (Field Programmable Gate Array);
• a second FPGA;
• an application software;
• and
• a communication interface to connect the second FPGA with the application software;
• a TAP interface module to sense a change in a plurality of data signals and capture the change in the plurality of data signals;
• wherein the second FPGA comprises:
• a monitor RTL (Register Transfer Level) for tapping the plurality of data signals from different levels of the first FPGA;
• a transaction based signal trigger for capturing the plurality of signals tapped at different levels of the monitor RTL;
• a monitor data interface for storing a plurality of data signals of interest, and wherein the plurality of data signals of interest are selected and captured based on a user-defined set of instructions;
• and
• a data packet for converting the plurality of signals to a plurality of packets and transmit the plurality of packets to the application software;
• an application layer for providing an information regarding each bit to a monitor data interface to report an application algorithm regarding an availability of the data, and wherein the application layer includes a control register interface through which bit positions of the plurality of data signals are intimated to the data packetizer;
• a monitor register interface for storing the bit positions of the plurality of data signals;
• wherein the application software decodes the plurality of transmitted packets and displays the transaction on a waveform viewer by communicating an information related to the packets using a plurality of communication protocols, and wherein the waveform viewer is an Electronic design Automation (EDA) waveform viewer for displaying the plurality of data signals of interest.