Watchpoint support system for functional simulator

A method for operating a functional simulator with watchpoint support, wherein the functional simulator is run by a front-end tool, the functional simulator including a central processing unit (CPU) having a first-level direct memory interface (DMI) cache, a watchpoint manager having a second-level DMI cache, and a memory controller, the method comprising:

• assigning a plurality of watchpoints to a first plurality of memory addresses by the front-end tool;
• adding the plurality of watchpoints to a watchpoint address list by the watchpoint manager, wherein the watchpoint address list is stored in the second-level DMI cache;
• invalidating a DMI access to the first-level DMI cache corresponding to a first plurality of memory pages associated with the first plurality of memory addresses, wherein the CPU invalidates the DMI access;
• setting a plurality of access bits negative to prevent the DMI access to the first plurality of memory pages during execution of a subsequent memory access request, wherein the plurality of access bits is set by the CPU;
• receiving a memory access request by the first-level DMI cache for a first memory address;
• transmitting the memory access request to the watchpoint manager by the CPU if the first-level DMI caches fails to complete the memory access request;
• searching for the first memory address associated with the memory access request in the watchpoint address list by the watchpoint manager;
• generating a watchpoint hit signal when the first memory address is present in the watchpoint address list;
• searching for the first memory address in the second-level DMI cache when the first memory address is not present in the watchpoint address list, wherein the second-level DMI cache stores a second plurality of memory pages and associated memory addresses of the first plurality of memory pages and associated memory addresses that are present in the first-level DMI cache;
• and
• transmitting the memory access request to the memory controller for completing the memory access request when the first memory address is absent from the second-level DMI cache.