US 9,176,816 B2Granted

Memory system configured to control data transfer

AssigneeKabushiki Kaisha Toshiba

InventorsJunji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira

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Abstract

A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.

Claims14

Dependent claims

A memory system, comprising:

a first semiconductor memory;
a second semiconductor memory into which data read out from the first semiconductor memory is written;
and
a controller configured to control the first semiconductor memory and the second semiconductor memory, wherein,
when reading out the data from the first semiconductor memory, the controller:
determines whether error correction for the data read out from the first semiconductor memory is successful, wherein,
when the error correction is successful, the controller:
stores, in the second semiconductor memory, corrected data of the data read out from the first semiconductor memory;
and
writes, in the first semiconductor memory, the corrected data of the data read out from the first semiconductor memory, wherein,
when the error correction is unsuccessful, the controller:
writes, in the first semiconductor memory, the data read out from the first semiconductor memory, without storing, in the second semiconductor memory, the corrected data of the data read out from the first semiconductor memory.

9 more elements

A memory system, comprising:

a nonvolatile first semiconductor memory;
a second semiconductor memory;
and
a controller configured to read out data from the first semiconductor memory, and write, in the second semiconductor memory, the data read out from the first semiconductor memory, wherein,
when reading out the data from the first semiconductor memory, the controller:
determines whether error correction for the data read out from the first semiconductor memory is successful, wherein
the controller:
stores, in the second semiconductor memory, data in which the error correction is successful;
writes, in the first semiconductor memory, the corrected data of the data read out from the first semiconductor memory;
and
writes, in the first semiconductor memory, the data read out from the first semiconductor memory, without storing, in the second semiconductor memory, data in which the error correction is unsuccessful.

8 more elements

A memory system, comprising:

a first semiconductor memory;
a second semiconductor memory;
and
a controller configured to read data from the first semiconductor memory, wherein,
when the data is corrected, the controller writes the data in the second semiconductor memory;
and
when the data is not corrected, the controller writes the data in the first semiconductor memory, without storing in the second semiconductor memory.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/262,405Filed 25 Apr 2014 · continuation
Priority: JP 2008-0514761 Mar 2008
Published: US 2014/0237320 A121 Aug 2014
Granted: 3 Nov 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G06F 11/1072
In individual solid state devices: in multilevel memories
G06F 3/0619
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Family

Application12/394,665Parent of this continuation · filed 27 Feb 2009
Application13/152,962Parent of this continuation · filed 3 Jun 2011
US 2014/0237320 A1Pre-grant publication · published 21 Aug 2014
US 8,751,901 B2Parent of this continuation
US 8,276,043 B2Parent of this continuation
US 2009/0241010 A1Published application
US 2011/0231734 A1Published application
US 9,176,816 B2This patent

From the US filing history. Foreign family members aren’t listed.