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US 9,176,741 B2Granted
Method and apparatus for segmented sequential storage
AssigneeThe Invention Science Fund I, LLC
InventorAndrew Forsyth Glew
Life of this patent
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Abstract
A method for sequential data storage. In an embodiment of such a method, a non-circular data structure is used for sequential data storage. The method includes dividing the non-circular data structure into a plurality of segments, where each segment includes a plurality of entries. The method further includes dynamically allocating the plurality of segments and sequentially associating the dynamically allocated segments.
Claims30
A method, comprising:
- providing a microprocessor, the microprocessor including at least:
- two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache;
- and
- an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage;
- dividing the inter-cluster second level stage into a plurality of segments;
- dynamically allocating the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;
- sequentially associating the first and second segments via one or more pointers;
- and
- responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, searching at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments,
- wherein the dividing, allocating, associating, and searching are implemented at least partially using at least one of (i) at least some hardware blocks of the provided microprocessor or (ii) at least some microcode of the provided microprocessor.
7 more elements
A microprocessor, comprising:
- one or more CPU cores including at least:
- two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache;
- an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage;
- and
- circuitry configured to at least:
- divide the inter-cluster second level stage into a plurality of segments;
- dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;
- sequentially associate the first and second segments via one or more pointers;
- and
- responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, search at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments,
- wherein the circuitry is at least partially implemented using at least one of (i) at least some hardware blocks of the microprocessor or (ii) at least some microcode of the microprocessor.
8 more elements
A microprocessor, comprising:
- at least one store of microcode;
- two or more execution clusters, at least two of the two or more execution clusters including at least one first level stage, the at least one first level stage including one or more of at least one store buffer, at least one register file, or at least one data cache;
- an inter-cluster second level stage, the inter-cluster second level stage operably coupled with at least one first level stage of at least two of the two or more execution clusters, the inter-cluster second level stage larger than a first level stage;
- and
- circuitry configured to execute at least some microcode of the at least one store to at least:
- divide the inter-cluster second level stage into a plurality of segments;
- dynamically allocate the plurality of segments, including at least allocating a first segment to at least receive at least one content of at least one first level stage of at least one execution cluster at a first time and allocating a second segment to at least receive at least one content of the at least one first level stage of the at least one execution cluster at a second time;
- sequentially associate the first and second segments via one or more pointers;
- and
- responsive to a request for at least a portion of the at least one content of the at least one first level stage at the first time, search at least the first segment and the second segment, including at least traversing the first and second segments via the one or more pointers associating the first and second segments.
7 more elements
Dependencies are inferred from the claim text.