System and method of indirect register access via directly accessible registers
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, Mark Jurenka, Gavin Huggins
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.
Claims17
A system comprising:
- a plurality of registers, wherein the plurality of registers comprises:
- a first set of registers directly accessible by a device;
- and
- a second set of registers indirectly accessible by the device solely via the first set of registers, wherein the first set of registers includes a first subset of registers that comprise a third register configured to enable indirect access to the second set of registers by the device based upon stored values in both a first register and a second register of the first subset of registers, wherein the first register, the second register, and the third register are independently accessible by the device separate from one another, wherein the first set of registers includes a second subset of registers different from the first subset;
- an access logic circuit configured to manage access to the first set of registers and the second set of registers, wherein the access logic circuit is configured to write to the first register, wherein the second register of the first set of registers is automatically set to a predetermined value when the access logic circuit writes to the first register;
- and
- a pattern-recognition processor, wherein the second set of registers are configured to store information related to the pattern-recognition processor, wherein the pattern-recognition processor comprises:
- a row decoder circuit having an input configured to receive a data stream to be searched;
- and
- a plurality of feature cells coupled to the row decoder circuit, wherein each of the plurality of feature cells comprises a plurality of memory cells, each memory cell addressable by a conductor coupled to an output of the row decoder circuit.
A method of processing data, the method comprising:
- reading bits from a first register of a first set of registers, wherein each unique value of the bits represents a unique auto-change mode from a plurality of auto-change modes;
- selecting a specified auto-change mode from a plurality of auto-change modes based on the bits from the first register, the selecting comprising:
- selecting, when the bits correspond to a first value, an auto-increment mode in which a first address stored in a second register of the first set of registers is incremented at the completion of a bus cycle;
- selecting, when the bits correspond to a second value, an auto-decrement mode in which a first address stored in the second register of the first set of registers is decremented at the completion of the bus cycle;
- and
- selecting, when the bits correspond to a third value, an auto-reset mode in which the second register is set to a predetermined value at the completion of the bus cycle;
- reading a given address from the second register of the first set of registers;
- accessing a first register of a second set of registers at the given address;
- and
- automatically modifying the given address based on the specified auto-change mode.
Dependencies are inferred from the claim text.