System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions

An apparatus, comprising:

• a bitwise exclusive OR (XOR) network;
• an indicator of a non-sequential fetch operation;
• and
• an error detection module, wherein the error detection module is configured to perform operations comprising:
• determining whether an instruction is a target of a non-sequential fetch operation;
• determining an expected numerical property value based on whether the instruction is the target of the non-sequential fetch operation;
• determining, using all bits in the instruction, whether a numerical property value of the instruction matches the expected numerical property value, wherein one bit encoded in a signed offset field of the instruction is a parity bit and is utilized, in part, to modulate the numerical property value;
• and
• avoiding an execution of the instruction when it is determined that the numerical property value of the instruction does not match the expected numerical property value.

Logic encoded in non-transitory media that includes code, which when executed by a processor performs operations comprising:

• determining whether an instruction is a target of a non-sequential fetch operation;
• determining an expected numerical property value based on whether the instruction is the target of the non-sequential fetch operation;
• determining, using all bits in the instruction, whether a numerical property value of the instruction matches the expected numerical property value, wherein one bit encoded in a signed offset field of the instruction is a parity bit and is utilized, in part, to modulate the numerical property value;
• and
• avoiding an execution of the instruction when it is determined that the numerical property value of the instruction does not match the expected numerical property value.