Load multiple and store multiple instructions in a microprocessor that emulates banked registers

A method for operating a microprocessor that supports the Advanced RISC Machines (ARM) instruction set architecture (ISA), which specifies a plurality of processor modes, including a User mode, an FIQ exception mode, and a non-FIQ exception mode, and which specifies architectural registers associated with each of the plurality of processor modes and which specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the method comprising:

• for each of the architectural registers specified by the load multiple instruction:
• when the architectural register is currently in the first portion, loading data from memory into direct storage of the microprocessor;
• and
• when the architectural register is currently in the second portion, loading data from memory into the direct storage and then storing the data from the direct storage to the indirect storage;
• wherein the direct storage holds data associated with a first portion of the architectural registers and is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• wherein the indirect storage holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the indirect storage is a private random access memory (PRAM) not within the instruction set architecture system memory space;
• wherein the architectural registers in the first and second portions vary dynamically based upon a current processor mode of the plurality of processor modes;
• wherein when the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ exception mode;
• wherein when the current processor mode is the ARM ISA FIQ exception mode then the direct storage holds data associated with the FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA processor mode previous to the current processor mode;
• and
• wherein when the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and exception modes other than the current non-FIQ exception mode and also holds the R8-R12 architectural registers of the ARM ISA FIQ exception mode.

A microprocessor that supports the Advanced RISC Machines (ARM) instruction set architecture (ISA), which specifies a plurality of processor modes, including a User mode, an FIQ exception mode, and a non-FIQ exception mode, and which specifies architectural registers associated with each of the plurality of processor modes and which specifies a store multiple instruction that instructs the microprocessor to store data to memory from one or more of the architectural registers specified by the store multiple instruction, the microprocessor comprising:

• direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the indirect storage is a private random access memory (PRAM) not within the instruction set architecture system memory space;
• wherein the architectural registers in the first and second portions vary dynamically based upon a current processor mode of the plurality of processor modes;
• and
• wherein for each of the architectural registers specified by the store multiple instruction:
• when the architectural register is currently in the first portion, the microprocessor stores data to memory from the direct storage;
• and
• when the architectural register is currently in the second portion, the microprocessor loads data from the indirect storage to the direct storage and then stores the data to memory from the direct storage;
• wherein when the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ exception mode;
• wherein when the current processor mode is the ARM ISA FIQ exception mode then the direct storage holds data associated with the FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA processor mode previous to the current processor mode;
• and
• wherein when the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and exception modes other than the current non-FIQ exception mode and also holds the R8-R12 architectural registers of the ARM ISA FIQ exception mode.

A method for operating a microprocessor that supports the Advanced RISC Machines (ARM) instruction set architecture (ISA), which specifies a plurality of processor modes, including a User mode, an FIQ exception mode, and a non-FIQ exception mode, and which specifies architectural registers associated with each of the plurality of processor modes and which specifies a store multiple instruction that instructs the microprocessor to store data to memory from one or more of the architectural registers specified by the store multiple instruction, the method comprising:

• for each of the architectural registers specified by the store multiple instruction:
• when the architectural register is currently in the first portion, storing data to memory from direct storage of the microprocessor;
• and
• when the architectural register is currently in the second portion, loading data from the indirect storage to the direct storage and then storing the data from the indirect storage to memory;
• wherein the direct storage holds data associated with a first portion of the architectural registers and is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• wherein the indirect storage holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the indirect storage is a private random access memory (PRAM) not within the instruction set architecture system memory space;
• wherein the architectural registers in the first and second portions vary dynamically based upon a current processor mode of the plurality of processor modes;
• wherein when the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ exception mode;
• wherein when the current processor mode is the ARM ISA FIQ exception mode then the direct storage holds data associated with the FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA processor mode previous to the current processor mode;
• and
• wherein when the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and exception modes other than the current non-FIQ exception mode and also holds the R8-R12 architectural registers of the ARM ISA FIQ exception mode.

A non-transitory computer readable storage medium encoding a computer program product for use with a computing device, the computer readable storage medium comprising:

• computer readable program code embodied in said medium, for specifying a microprocessor that supports the Advanced RISC Machines (ARM) instruction set architecture (ISA), which specifies a plurality of processor modes, including a User mode, an FIQ exception mode, and a non-FIQ exception mode, and which specifies architectural registers associated with each of the plurality of processor modes and which specifies a load multiple instruction that instructs the microprocessor to load data from memory into one or more of the architectural registers specified by the load multiple instruction, the computer readable program code comprising:
• first program code for specifying direct storage, that holds data associated with a first portion of the architectural registers and that is coupled to at least one execution unit of the microprocessor to provide the data to the execution unit;
• and
• second program code for specifying indirect storage, that holds data associated with a second portion of the architectural registers, wherein the indirect storage is incapable of directly providing the data associated with the second portion of the architectural registers to the at least one execution unit;
• wherein the indirect storage is a private random access memory (PRAM) not within the instruction set architecture system memory space;
• wherein the architectural registers in the first and second portions vary dynamically based upon a current processor mode of the plurality of processor modes;
• wherein for each of the architectural registers specified by the load multiple instruction:
• when the architectural register is currently in the first portion, the microprocessor loads data from memory into the direct storage;
• and
• when the architectural register is currently in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage;
• wherein when the current processor mode is the ARM ISA User mode then the direct storage holds data associated with the User mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA exception modes and the R8-R12 architectural registers of the ARM ISA FIQ exception mode;
• wherein when the current processor mode is the ARM ISA FIQ exception mode then the direct storage holds data associated with the FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and non-FIQ exception modes and the R8-R12 architectural registers of the ARM ISA processor mode previous to the current processor mode;
• and
• wherein when the current processor mode is an ARM ISA non-FIQ exception mode then the direct storage holds data associated with the non-FIQ exception mode architectural registers, and the indirect storage holds data associated with the R13-R14 architectural registers of the ARM ISA User mode and exception modes other than the current non-FIQ exception mode and also holds the R8-R12 architectural registers of the ARM ISA FIQ exception mode.