Shared integer, floating point, polynomial, and vector multiplier

An execution unit comprising four multipliers, wherein each multiplier comprises an adder tree and a plurality of encoders, wherein each adder tree comprises three levels of carry save adders (CSAs), wherein a top level comprises three CSAs, wherein a middle level comprises two CSAs, wherein a bottom level comprises one CSA, and wherein each adder tree is configured to:

• couple output values from the plurality of encoders to inputs of the three CSAs on the top level;
• couple carry outputs from the three CSAs on the top level to inputs of a first CSA on the middle level;
• couple sum outputs from the three CSAs on the top level to inputs of a second CSA on the middle level;
• wherein each encoder of the plurality of encoders is configured to:
• generate an encoder output value based on three bits from a multiplier operand when operating in a first mode;
• and
• generate the encoder output value based on two bits from the multiplier operand and force a third bit of the multiplier operand to zero when operating in a second mode, wherein the two bits and the third bit are three distinct bits,
• wherein the second mode is a polynomial multiplication mode.

A method comprising:

• generating a sum term and a carry term in each CSA of three top-level CSAs of an adder tree;
• conveying the three carry terms to a first middle-level CSA of the adder tree;
• conveying the three sum terms to a second middle-level CSA of the adder tree;
• generating a sum term and a carry term in the first middle-level CSA;
• generating a sum term and a carry term in the second middle-level CSA, wherein the sum term is a polynomial product of a multiplicand operand and a multiplier operand;
• generating an encoder output value from each of a plurality of encoders based on three bits from a multiplier operand when operating in a first mode;
• generating the encoder output value from each of the plurality of encoders based on two bits from the multiplier operand and forcing a third bit of the multiplier operand to zero when operating in a second mode, wherein the two bits and the third bit are three distinct bits, and
• conveying the encoder output values to inputs of the three top-level CSAs of the adder tree,
• wherein the second mode is a polynomial multiplication mode.

A method comprising:

• generating a plurality of encoder output values, wherein each encoder output value of the plurality of encoder output values is generated based on three adjacent bits of a multiplier operand responsive to a first mode being selected, and wherein each encoder output value is generated based on two adjacent bits of the multiplier operand and a third bit of the multiplier operand is forced to zero responsive to a second mode being selected, wherein the two adjacent bits and the third bit are three distinct bits;
• generating a plurality of partial products from a multiplicand operand;
• for each encoder output value, selecting a partial product from the plurality of partial products based on a respective encoder output value;
• conveying the plurality of selected partial products to an adder tree;
• generating a plurality of sum outputs and a plurality of carry outputs on a top level of the adder tree;
• and
• adding the plurality of sum outputs separately from the plurality of carry outputs on successive levels of the adder tree,
• generating a first output from the adder tree responsive to operating in the first mode;
• and
• generating a second output from the adder responsive to operating in the second mode, wherein the second output is a polynomial product.