Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system

A memory sub-system, comprising:

• NAND flash memory;
• dynamic random access memory;
• a first circuit for receiving and processing DDR signals such that the DDR signals result in SATA signals, the first circuit including embedded dynamic random access memory, the first circuit capable of being communicatively coupled to a first memory bus including a standard bus associated with a DDR protocol including at least one of a DDR protocol, a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol;
• and
• a second circuit for receiving and processing the SATA signals such that the SATA signals result in NAND flash signals, the second circuit communicatively coupled to the first circuit via a second memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the dynamic random access memory;
• wherein the memory sub-system is configured for:
• receiving, at the first circuit and via the standard bus, a special command associated with a first thread utilizing the DDR protocol, the special command being one of a plurality of commands from a processing unit or a system component required for a random access data read from the NAND flash memory via the embedded dynamic random access memory;
• providing a status;
• and
• after the status, receiving, at the first circuit, a read command utilizing the DDR protocol, the read command being another one of the plurality of commands from the processing unit or the system component required for completing the random access data read from the NAND flash memory via the embedded dynamic random access memory;
• wherein the memory sub-system is further configured for causing data to be fetched between the first thread and a second thread.

An apparatus, comprising:

• a memory sub-system including:
• NAND flash memory;
• random access memory;
• first circuitry for receiving DDR signals and outputting SATA signals, the first circuitry capable of receiving the DDR signals from a first memory bus including a DDR bus associated with a DDR protocol including at least one of a DDR protocol, a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol;
• and
• second circuitry for receiving the SATA signals and outputting NAND flash signals, the second circuitry in communication with the first circuitry via a second memory bus associated with a SATA protocol, the second circuitry in communication with the NAND flash memory via a third memory bus associated with a NAND flash protocol;
• wherein the first circuitry is operable for:
• receiving a command that is special and is associated with a first thread via the DDR bus, the command that is special being one of a plurality of commands that are required for a random access data read involving the NAND flash memory and the random access memory;
• providing a status;
• after the status, receiving a read command via the DDR bus, the read command being another one of the plurality of commands that are required for the random access data read involving the NAND flash memory and the random access memory;
• and
• causing data associated with the random access data read to be fetched between the first thread and a second thread.