Address resource mapping in a shared memory computer system
AssigneeSilicon Graphics International Corp.
InventorsBrian Justin Johnson, Michael John Habeck
Life of this patent
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Abstract
An algorithm for mapping memory and a method for using a high performance computing (“HPC”) system are disclosed. The algorithm takes into account the number of physical nodes in the HPC system, and the amount of memory in each node. Some of the nodes in the HPC system also include input/output (“I/O”) devices like graphics cards and non-volatile storage interfaces that have on-board memory; the algorithm also accounts for the number of such nodes and the amount of I/O memory they each contain. The algorithm maximizes certain parameters in priority order, including the number of mapped nodes, the number of mapped I/O nodes, the amount of mapped I/O memory, and the total amount of mapped memory.
Claims21
A computer system having hardware-based non-uniform memory access, the computer system comprising a plurality of nodes, each node having a volatile memory and at least one computing processor, each computing processor being capable of addressing a maximum amount of volatile memory that is less than the collective amount of volatile memory in the plurality of nodes, wherein at least one node also includes an I/O device having I/O memory, each node being configured to calculate a memory layout that includes a portion of the volatile memory of each of a plurality of nodes in the computer system, the memory layout being calculated to minimize an amount of unmapped memory as a function of 1) the number of nodes in the computer system, 2) the amount of volatile memory in each node, 3) the number of nodes that include an I/O device having I/O memory, and 4) the amount of I/O memory in each such I/O device, wherein the computing processor of each node is further configured to access the memory of another node using the calculated memory layout.
A method of operating a computer system having hardware-based non-uniform memory access, the computer system having a plurality of nodes, each node having a volatile memory and at least one computing processor, each computing processor being capable of addressing a maximum amount of volatile memory that is less than the collective amount of volatile memory in the plurality of nodes, wherein at least one node also includes an I/O device having I/O memory, the method comprising:
- in each node of the computer system, calculating a memory layout that includes a portion of the volatile memory of each of a plurality of nodes in the computer system, the memory layout being calculated to minimize an amount of unmapped memory as a function of 1) the number of nodes in the computer system, 2) the amount of volatile memory in each node, 3) the number of nodes that include an I/O device having I/O memory, and 4) the amount of I/O memory in each such I/O device;
- and
- accessing, by a computing processor in a first node of the computer system, the memory of a second node of the computer system using the calculated memory layout.
A computer program product for operating a computer system having hardware-based non-uniform memory access, the computer system having a plurality of nodes, each node having a volatile memory and at least one computing processor, each computing processor being capable of addressing a maximum amount of volatile memory that is less than the collective amount of volatile memory in the plurality of nodes, wherein at least one node also includes an I/O device having I/O memory, the computer program product comprising a non-transitory, tangible computer-readable storage medium on which is stored non-transitory program code for:
- instructing each node of the computer system to calculate a memory layout that includes a portion of the volatile memory of each of a plurality of nodes in the computer system, the memory layout being calculated to minimize an amount of unmapped memory as a function of 1) the number of nodes in the computer system, 2) the amount of volatile memory in each node, 3) the number of nodes that include an I/O device having I/O memory, and 4) the amount of I/O memory in each such I/O device;
- and
- instructing a computing processor in a first node of the computer system to access the memory of a second node of the computer system using the calculated memory layout.
Dependencies are inferred from the claim text.