System and method for providing universal serial bus link power management policies in a processor environment
AssigneeIntel Corporation
InventorJaya L. Jeyaseelan
Life of this patent
Estimating the term…
Abstract
One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value.
Claims30
An apparatus, comprising:
- logic, at least a portion of which is in hardware, the logic configured to:
- determine that a first device maintains a link to a platform in a selective suspend state;
- assign a first latency value to the first device;
- identify at least one user detectable artifact when a second device exits the selective suspend state;
- and
- assign, to the second device, a second latency value that is different from the first value.
A system, comprising:
- a device controller;
- and
- a platform power management controller, wherein the system is configured for:
- determining that a first device maintains a link in a selective suspend state;
- assigning a first latency value to the first device;
- identifying at least one user detectable artifact when a second device exits the selective suspend state;
- and
- assigning, to the second device, a second latency value that is different from the first latency value.
A non-transitory computer readable medium comprising instructions that, when executed, cause an apparatus to:
- determine that a first device maintains a link to a platform in a selective suspend state;
- assign a first latency value to the first device;
- identify at least one user detectable artifact when a second device exits the selective suspend state;
- and
- assign, to the second device, a second latency value that is different from the first value.
An apparatus, comprising:
- a circuit configured for:
- determining that a first device maintains a link to a platform in a selective suspend state;
- assigning a first latency value to the first device;
- identifying at least one user detectable artifact when a second device exits the selective suspend state;
- and
- assigning, to the second device, a second latency value that is different from the first latency value.
Dependencies are inferred from the claim text.