Debug architecture

#This application claims the benefit of prior United Kingdom Patent Application No. GB 1212179.4, filed Jul. 9, 2012, entitled “DEBUG ARCHITECTURE,” which application is incorporated herein by reference in its entirety.

#This disclosure relates to debugging peripheral circuits, such as processors, on an integrated circuit chip. The disclosure is particularly relevant to debugging peripheral circuits which form part of a System-on-Chip (SoC).

#In the past, an embedded system which had multiple core devices (processors, memories etc.) would have been incorporated onto a Printed Circuit Board (PCB) and connected on the PCB via buses. Traffic in the embedded system was conveyed over these buses. This arrangement was convenient for debugging the core devices, because debugging tools such as oscilloscopes and logic analyzers could be attached to the PCB's buses allowing direct access to the core devices.

#The present disclosure will now be described by way of example with reference to the accompanying drawings. In the drawings:

#FIG. 1 is a schematic diagram of an exemplary debug architecture;

#FIG. 2 is a schematic diagram of an exemplary shared hub;

#The following disclosure describes a debug architecture suitable for implementation on a SoC. The debug architecture enables debugging of the whole SoC rather than just individual core devices.

#FIGS. 1, 2, 3, 7, 8 and 9 are schematic diagrams of exemplary debug architectures, and components within debug architectures. These figures present the structures in terms of functional blocks. Some functional blocks for carrying out functions well known in the art have in places been omitted from these figures.

#FIG. 1 illustrates the general structure of an exemplary debug architecture for a SoC 100. Core devices 102, 104 and 106 of the SoC are each respectively connected to their own debug units 108, 110 and 112. Although FIG. 1 illustrates three core devices, any number of core devices can be suitably integrated into the debug architecture. Exemplary core devices include a DSP (digital signal processor), video processor, applications processor graphics processor, system memory, bus, system interconnect, RTOS (real-time operating system), software, data, custom circuit and a data engine. However, any component of a SoC is suitable for being incorporated into the debug architecture as a core device on FIG. 1. The core devices may be emulators or simulators of other devices on the chip. For example, a core device may emulate a processor. The debug unit associated with a core device interfaces that core device.