Tunable delay cells for time-to-digital converter

A delay unit structure, comprising:

• a first delay unit that includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor, wherein the tunable PMOS transistor and the first PODE transistor share a same source as each other;
• a second delay unit that includes a tunable NMOS transistor, a second PODE transistor, and a pull-down PMOS transistor, wherein the tunable NMOS transistor and the second PODE transistor share a same source as each other;
• wherein gates of the first and the second delay units are each coupled to an adjustable voltage source to provide a DC bias on the gates of the delay units.

A method for forming a time-to-digital converter (TDC), comprising:

• forming a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor;
• forming a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor;
• implementing at least one of the first delay units and at least one of the second delay units on a same oxide definition (OD) region.