System and method for decomposition of a single photoresist mask pattern into 3 photoresist mask patterns

A method of decomposing a single photoresist mask pattern to three photoresist mask patterns, comprising:

• assigning, by a processor, nodes to polygon features on the single photoresist mask pattern;
• designating nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, the predetermined distance being derived from a property of semiconductor processing equipment for fabrication of a semiconductor device;
• iteratively removing nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain and one or more internal nodes remain;
• determining a decomposability of the single photoresist mask pattern to three photoresist mask patterns based on the one or more internal nodes, wherein determining the decomposability comprises making a decomposability assessment of each internal node of the one or more internal nodes independent of decomposability assessments of other internal nodes of the one or more internal nodes;
• mapping colors to the one or more internal nodes;
• replacing and mapping a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color, and
• generating, based on the replacing and mapping, a layout design for fabrication of the semiconductor device.

A single photoresist mask pattern to a plurality of photoresist mask patterns decomposition system, the system comprising:

• one or more instructions stored on a non-transitory computer-readable medium;
• a processor configured to execute the one or more instructions, for causing the processor to perform:
• assigning nodes to polygon features on the single photoresist mask pattern,
• designating nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, the predetermined distance being derived from a property of semiconductor processing equipment for fabrication of a semiconductor device,
• iteratively removing nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain and one or more internal nodes remain,
• determining a decomposability of the single photoresist mask pattern to the plurality of photoresist mask patterns based on the one or more internal nodes, wherein determining the decomposability comprises making a decomposability assessment of each internal node of the one or more internal nodes independent of decomposability assessments of other internal nodes of the one or more internal nodes,
• mapping colors to the one or more internal nodes,
• replacing and mapping a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color,
• providing an indication of the decomposability of the single photoresist mask pattern to the plurality of photoresist mask patterns, and
• generating, based on the replacing and mapping, a layout design for fabrication of the semiconductor device;
• and
• a memory storing information describing an order of iteratively removing nodes by the processor.