Pixel array and liquid crystal display device

A pixel array, comprising:

• pixel units, data lines quantitatively corresponding to the number of columns N of the pixel units, and scan lines quantitatively corresponding to the number of rows of the pixel units, wherein
• transistors in the pixel units are arranged in the same direction;
• the pixel units in a same row are connected to the same scan line;
• the pixel units in each column and in odd rows are connected respectively to corresponding one of the data lines;
• the pixel units in each column and in even rows are connected respectively to corresponding one of the data lines;
• and
• the pixel units in the nth column in and even rows and the pixel units in the (n−1)th column and in odd rows are connected to the same data line, where n=2, . . . , N.

A liquid crystal display device, comprising:

• a pixel array, a scan drive circuit and a data drive circuit;
• wherein
• the pixel array comprises pixel units, data lines quantitatively corresponding to the number of columns N of the pixel units, and scan lines quantitatively corresponding to the number of rows of the pixel units, wherein
• transistors in the pixel units are arranged in a same direction;
• the pixel units in a same row are connected to the same scan line;
• the pixel units in each column and in odd rows are connected respectively to corresponding one of the data lines;
• the pixel units in each column and in even rows are connected respectively to corresponding one of the data lines;
• and
• the pixel units in the nth column and in even rows and the pixel units in the (n+1)th column and in odd rows are connected to the same data line, where n=1, 2, . . . , N−1;
• the scan drive circuit is connected to the scan lines and adapted to provide corresponding scan signals to the scan lines, and the data drive circuit is connected to the data lines and adapted to provide corresponding data signals to the data lines.

A pixel array, comprising:

• N data lines arranged in columns;
• M scan lines arranged in rows;
• N*M transistors forming N*M pixel units disposed along intersections of the N data lines and M scan lines;
• wherein a first half of M transistors associated with at least a first pair of adjacent data lines have drain regions positioned on a first side of one of the at least first pair of the adjacent data lines to define a first pixel column;
• and
• wherein a second half of M transistors associated with the at least first pair of adjacent data lines have drain regions positioned on the first side of the other one of the at least first pair of the adjacent data lines to define a second pixel column.