# US 9,172,394 B2 · Signal conversion system and method

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- Number: US 9,172,394 B2
- Document ID: US9172394B2
- Status: Granted
- Kind: B2
- Application number: 14/382,979
- Filed: 2013-03-06
- Published: 2015-01-15
- Granted: 2015-10-27
- Earliest claimed: 2012-03-07
- Assignees: Actiwave AB
- Applicants: Actiwave AB
- Inventors: Erik Lindahl; Pär Gunnars Risberg
- Web page: https://patentgrep.com/patent/US9172394B2

## CPC

- H03K 7/08: Duration or width modulation {; Duty cycle modulation}
- H03K 9/08: of duration- or width-mudulated pulses {or of duty-cycle modulated pulses}
- H03M 3/506: {the final digital/analogue converter being constituted by a pulse width modulator}
- H03M 5/08: Code representation by pulse width
- H04L 25/4902: {Pulse width modulation; Pulse position modulation}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.

## Claims

### Claim 1

A signal conversion system for converting an input signal to a pulse width modulated (PWM) output signal comprising:
a clock source for generating and/or for accepting a clock signal;
a carrier generator configured to generate a carrier signal with a carrier signal frequency;
a cross-point section (CPS) block comprising a CPS comparator to compare the carrier signal to the input signal or a signal derived therefrom to produce a triggered signal based on the comparison and the input signal or the signal derived therefrom;
a noise shaper configured to bit depth reduce the triggered signal to form a truncated signal;
a PWM comparator configured to compare the truncated signal and/or a signal generated therefrom with the carrier signal to produce the PWM output signal; and
a sample rate converter comprising a counter configured to generate a count-disparity signal from the clock signal and the input signal, a first sigma delta unit configure to calculate a temporal correction value from the count disparity signal, a resampled clock generator configured to generate one or more resampled clock signals from the temporal correction value, and a second sigma delta unit configured to generate the resampled signal from one or more of the resampled clock signals and the input signal.

### Claim 2 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the sample rate converter is configured to resample the input signal to a resampled signal with a sample rate greater than the carrier signal frequency, wherein the CPS comparator is configured to accept the resampled signal.

### Claim 3 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the noise shaper is configured to shift the noise on the triggered signal, the input signal, and/or the resampled signal to a substantially inaudible frequency band to form the truncated signal.

### Claim 4 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the noise shaper includes an nth order delta-sigma modulator configured to perform the bit depth reduction and/or noise shifting, and wherein n is a positive integer.

### Claim 5 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the noise shaper includes a threshold of hearing model.

### Claim 6 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the carrier generator is configured to accept a phase correction parameter, and wherein the carrier signal is dependent upon the phase correction parameter.

### Claim 7 (depends on 6)

The signal conversion system in accordance with claim 6, wherein the phase correction parameter is configured to set an initial value for the carrier signal.

### Claim 8 (depends on 1)

The signal conversion system in accordance with claim 1, further comprising an analyzer configured to accept the input signal, the resampled signal or a signal generated therefrom and/or an external input and to calculate a PWM control signal, wherein the carrier generator, the PWM comparator, and/or the noise shaper is configured to accept the PWM control signal.

### Claim 9 (depends on 8)

The signal conversion system in accordance with claim 8, wherein the analyzer is configured to calculate a power level from at least a portion of the resampled signal or a signal generated therefrom, and wherein the PWM control signal is dependent upon the power level.

### Claim 10 (depends on 8)

The signal conversion system in accordance with claim 8, wherein the analyzer is configured to accept an external input at least partially representative of a property selected from the group consisting of temperature, humidity, sound level, loudspeaker feedback, voltage level, transducer current level, speaker enclosure temperature, speaker enclosure pressure level, and/or a combination thereof.

### Claim 11 (depends on 1)

The signal conversion system in accordance with claim 1, further comprising a FIFO buffer coupled to the counter and the input signal and configured to store successive samples of the input signal and the count-disparity signal.

### Claim 12 (depends on 11)

The signal conversion system in accordance with claim 11, further comprising an averaging block, coupled to the counter or the FIFO buffer and the first sigma delta loop, and configured to calculate an averaged count-disparity signal from the count disparity signal, wherein the first sigma delta loop is configured to accept the averaged count-disparity signal.

### Claim 13 (depends on 1)

The signal conversion system in accordance with claim 1, wherein the resampled clock generator is configured to resample the input signal to form a de-jittered signal having a substantially stabilized sample rate.

### Claim 14 (depends on 13)

The signal conversion system in accordance with claim 13, further comprising a low pass filter coupled to the resampled clock generator and the second sigma delta loop, wherein the low pass filter is configured to accept one or more resampled clock signals and the input signal or the de-jittered signal, and to calculate a filtered intermediate signal, and wherein the second sigma delta loop is configured to accept the filtered intermediate signal.

### Claim 15

A signal conversion system for converting an input signal to a pulse width modulated (PWM) signal comprising:
a clock source for generating and/or for accepting a clock signal;
a cross enable unit configured to generate one or more resampled clock signals and a de-jittered signal from the input signal and the clock signal;
a linear interpolation unit configured to generate a resampled signal from the de-jittered signal, the clock signal, and one or more of the resampled clock signals; and
a pulse width modulation (PWM) module comprising a carrier generator to generate a carrier signal, and a PWM comparator configured to compare the resampled signal or a signal derived therefrom and the carrier signal to form the PWM signal.

### Claim 16 (depends on 15)

The signal conversion system in accordance with claim 15, further comprising a FIR filter module including a low pass filter, the FIR filter module configured to generate a filtered intermediate signal from the de-jittered signal, the clock signal, and one or more of the resampled clock signals, wherein the linear interpolation unit is configured to accept the filtered intermediate signal.

### Claim 17 (depends on 15)

The signal conversion system in accordance with claim 15, wherein the cross enable unit comprises:
a counter configured to generate a count-disparity signal from the clock signal and the input signal;
a first sigma delta unit configured to calculate a temporal correction value from the count-disparity signal; and
a resampled clock generator configured to generate the one or more resampled clock signals from the temporal correction value.

### Claim 18 (depends on 17)

The signal conversion system in accordance with claim 17, wherein the cross enable unit comprises a FIFO buffer configured to store at least a sample of the count-disparity signal and input signal, and to release the sample to the first sigma delta loop.

### Claim 19

A method for generating a pulse width modulated (PWM) signal from an input signal and a clock signal both with respective sample rates comprising:
calculating a count disparity signal from the input signal and the clock signal, the count disparity signal relating to the difference in sampling rate between the clock signal and the input signal;
generating a temporal correction signal from the count-disparity signal, the temporal correction signal corresponding to a new sample rate, different from the input signal sample rate or the clock signal sample rate;
interpolating the input signal at the new sample rate to form a resampled signal;
forming a carrier signal with an initial value; and
comparing the resampled signal or a signal generated therefrom with the carrier signal to form the PWM signal.

### Claim 20 (depends on 19)

The method in accordance with claim 19, further comprising:
comparing the input signal, the resampled signal, or a signal generated therefrom with the carrier signal to form a triggered signal;
truncating the triggered signal to form a truncated signal; and
using the truncated signal in the comparison.

### Claim 21 (depends on 19)

The method in accordance with claim 19, wherein the step of generating a temporal correction signal is at least partially accomplished by using a first sigma delta loop.

### Claim 22 (depends on 19)

The method in accordance with claim 19, wherein the step of interpolating the input signal is at least partially accomplished by using a second sigma delta loop.

### Claim 23 (depends on 19)

The method in accordance with claim 19, further comprising adding a non-periodic signal to the count-disparity signal.

### Claim 24 (depends on 19)

The method in accordance with claim 19, further comprising shifting the noise of the resampled signal or a signal derived therefrom into a substantially inaudible frequency band.