Strained structure of semiconductor device and method of making the strained structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Cheng-Yi Peng, Clement Hsingjen Wann
Life of this patent
Estimating the term…
Abstract
An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.
Claims20
A field effect transistor (FET) comprising:
- a silicon substrate comprising a first surface;
- a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, a length parallel to the first surface, and the channel portion is a germanium channel portion;
- and
- two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material,
- wherein a portion of each of the two S/D regions extending downward from the second surface is lower than the first surface, thereby defining a second height greater than the first height.
A semiconductor device comprising:
- a silicon substrate comprising a first surface;
- a first channel portion and a second channel portion over the first surface, wherein each channel portion has a second surface at a first height above the first surface, and a length parallel to the first surface;
- a first field effect transistor (FET) comprising first two source/drain (S/D) regions on the first surface and surrounding the first channel portion along the length of the first channel portion, wherein the first two S/D regions comprise SiGe, Ge, GeSn, SiGeSn, SiSn, or III-V material;
- and
- a second FET comprising second two S/D regions on a third surface and surrounding the second channel portion along the length of the second channel portion, wherein the third surface is between the first surface and second surface, wherein the second two S/D regions comprise SiGe, Si, or SiC,
- wherein a portion of each of the first two S/D regions extending downward from the second surface is lower than the first surface, thereby defining a second height greater than the first height.
A semiconductor device comprising:
- a substrate comprising a first surface;
- a first field effect transistor (FET) on the first surface, the first FET comprising:
- a first channel portion over the first surface,
- first source/drain (S/D) regions on the substrate surrounding the first channel portion along a length of the first channel portion, the first S/D regions having a first height from a second, upper surface to downward extensions lower than the first surface;
- and
- a second FET on the first surface, the second FET comprising:
- a second channel portion over the first surface,
- second S/D regions on the substrate surrounding the second channel portion along a length of the second channel portion, the second S/D regions having a second height different from the first height.
Dependencies are inferred from the claim text.