Modulation through differentially delayed clocks

A method comprising:

• receiving a first clock signal;
• receiving a first baseband signal;
• generating a first delayed clock signal based, at least in part, on the first baseband signal and the first clock signal;
• generating a second delayed clock signal based, at least in part, on the first baseband signal and the first clock signal, wherein the first delayed clock signal is different from the second delayed clock signal;
• and
• combining the first delayed clock signal and the second delayed clock signal to generate a modulated clock signal.

A system comprising:

• a modulator for generating a modulated clock signal, the modulator comprising:
• a first configurable delay unit configured to receive a first clock signal and a first baseband signal and to generate a first delayed clock signal based, at least in part, on the first baseband signal,
• a second configurable delay unit configured to receive the first clock signal and the first baseband signal and to generate a second delayed clock signal based, at least in part, on the first baseband signal wherein the second delayed clock signal is different from the first delayed clock signal, and
• a combiner configured to generate the modulated clock signal based, at least in part, on the first delayed clock signal and the second delayed clock signal.

A non-transitory machine-readable storage media having machine executable instructions stored therein, the machine executable instructions comprising instructions to:

• receive a first clock signal;
• receive a first baseband signal;
• generate a first delayed clock signal with a first delay amount based, at least in part, on the first baseband signal and the first clock signal;
• generate a second delayed clock signal with a second delay amount based, at least in part, on the first baseband signal and the first clock signal, wherein the first delay amount is different from the second delay amount;
• and
• combine the first delayed clock signal and the second delayed clock signal to generate a modulated clock signal.