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US 9,166,541 B2Granted
Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier
AssigneeRenesas Electronics Corporation
InventorsYoshihiro Funato, Toshio Kumamoto, Tomoaki Yoshizawa, Kazuaki Kurooka
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Abstract
A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
Claims18
A signal processing circuit, comprising:
- a chopper amplifier that generates a chopper output signal by amplifying differential input signals;
- and
- an adder circuit that generates an addition signal by addition of the chopper output signal,
- wherein the chopper amplifier includes a differential amplifier circuit that amplifies the differential input signals, and the differential input signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period of a control clock,
- wherein the chopper amplifier generates the chopper output signal on which a non-inversion offset voltage and an inversion offset voltage are superimposed, respectively, in the first phase period and in the second phase period, and
- wherein the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
3 more elements
A resolver digital converter, comprising:
- a signal processing circuit that converts differential input signals generated based on a sine wave output and a cosine wave output of a resolver into an error determination signal between an angle signal of the resolver and a digital angle signal and outputs the error determination signal,
- wherein the signal processing circuit includes:
- a chopper amplifier for generating a chopper output signal by amplifying the differential input signals;
- an adder circuit for generating an addition signal by addition of the chopper output signal;
- and
- a comparator for generating the error determination signal using the addition signal,
- wherein the chopper amplifier has a differential amplifier circuit for amplifying the differential input signals, and the differential input signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period of a control clock,
- wherein the chopper amplifier generates the chopper output signal on which a non-inversion offset voltage and an inversion offset voltage are superimposed in the first phase period and in the second phase period, respectively, based on an output of the differential amplifier circuit, and
- wherein the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
6 more elements
A multipath nested mirror amplifier, comprising:
- a signal processing circuit to which differential input signals are applied and that outputs a first output signal;
- a second amplifier to which the differential input signals are applied and that outputs a second output signal;
- a third amplifier to which the second output signal is applied and that outputs a third output signal;
- a first capacitive element;
- and
- a second capacitive element,
- wherein the signal processing circuit includes:
- a chopper amplifier that generates a chopper output signal by amplifying the differential input signals;
- an adder circuit that generates an addition signal by addition of the chopper output signal;
- and
- a first amplifier that outputs the first output signal by amplifying the addition signal,
- wherein the chopper amplifier includes a differential amplifier circuit that amplifies the differential input signals, the differential input signals inputted into the differential amplifier circuit being interchanged for every first phase period and second phase period of a control clock,
- wherein the chopper amplifier generates the chopper output signal on which a non-inversion offset voltage and an inversion offset voltage are superimposed in the first phase period and in the second phase period, respectively, based on an output of the differential amplifier circuit,
- wherein the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period,
- wherein the first amplifier outputs the first output signal by amplifying the addition signal,
- wherein the second amplifier outputs the second output signal by amplifying the differential input signals,
- wherein the third amplifier outputs a third output signal by amplifying a signal such that the first output signal, the second output signal, and the third output signal fed back through the first capacitive element are added, and
- wherein the third amplifier feeds back the third output signal to an input terminal of the adder circuit through the second capacitive element.
15 more elements
Dependencies are inferred from the claim text.