US 9,165,793 B1Granted

Making electrical components in handle wafers of integrated circuit packages

AssigneeInvensas Corporation

InventorsLiang Wang, Hong Shen, Rajesh Katkar

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Claims20

Dependent claims

A method for making an integrated circuit package, the method comprising:

providing a handle wafer having a first region and a second region, the first region at least partially defining a cavity within the handle wafer, the cavity defining the second region;
forming a capacitor in the first region of the handle wafer, the capacitor having a pair of electrodes, each electrode being electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which is disposed on a lower surface of the handle wafer in the first region thereof;
providing an interposer having an upper surface with an electroconductive pad and a semiconductor die disposed thereon, the die having an integrated circuit (IC) formed therein, the IC being electroconductively coupled to a redistribution layer (RDL) disposed on or within the interposer;
and
bonding the lower surface of the handle wafer to the upper surface of the interposer such that the semiconductor die is disposed below or within the cavity of the handle wafer and the at least one electroconductive pad of the handle wafer is electroconductively bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

2 more elements

An integrated circuit package, comprising:

a first substrate having a first region and a second region, the first region at least partially defining a cavity within the substrate, the cavity defining the second region;
a capacitor formed in the first region of the first substrate, the capacitor comprising a layer of a dielectric sandwiched between a pair of electroconductive plates, each plate being electroconductively coupled to a corresponding one of a pair of electroconductive pads, at least one of which is disposed on the lower surface of the first substrate in the first region thereof;
and,
a second substrate having an upper surface with an electroconductive pad and a semiconductor die disposed thereon, the die having an integrated circuit (IC) formed therein, the IC being electroconductively coupled to a redistribution layer (RDL) disposed on or within the second substrate, wherein
the lower surface of the first substrate is bonded to the upper surface of the second substrate such that the die is disposed below or within the cavity and the at least one electroconductive pad of the first substrate is electroconductively bonded to the electroconductive pad of the second substrate in a metal-to-metal bond.

2 more elements

Dependencies are inferred from the claim text.