Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features

A method of semiconductor memory device operation, the method comprising:

• receiving, with a self-timed pulse generator, a clock signal;
• generating, with the self-timed pulse generator, a self-timed pulse having a first edge corresponding to a rising edge of the clock signal and a second edge;
• receiving, with a first input latch circuit, the self-timed pulse and a memory operation command;
• generating, with the first input latch circuit, an internal memory operation command set to a latched state corresponding to the first edge of the self-timed pulse;
• receiving, with a read and write control circuit, the self-timed pulse and internal memory operation signal;
• performing, with the read and write control circuit, a read operation and a write operation, the read operation being performed corresponding to one of the first edge and second edge of the self-timed pulse, and the write operation being performed corresponding to the one of the first edge and second edge of the self-timed pulse that does not correspond to the read operation;
• receiving, with a second input latch circuit, the self-timed pulse and a memory address;
• and
• generating, with the second input latch circuit, an internal address signal set to a latched state corresponding to the first edge of the self-timed pulse;
• wherein fast address access for read and write is provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from the control circuit.