Power measurement device
AssigneeSmart Energy Instruments Inc.
InventorDonald Jeffrey Dionne
Life of this patent
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Abstract
A power measurement device for sampling current or voltage signals of a power system to produce a 1-bit delta-sigma bitstream. The power measurement device includes a frequency locked loop for determining the power system frequency directly from the 1-bit delta-sigma bitstream. The frequency locked loop includes a 1-bit rotate CORDIC that is configured to produce difference signals having a multi-bit word for each bit of the 1-bit delta-sigma bitstream, and a phase error calculator that determines the difference between the phase of the power system frequency and a phase ramp generated from a frequency measurement value in a frequency register. The phase error calculator feeds back a phase correction signal to the frequency register to lock the frequency measurement value to the power system frequency.
Claims10
A power measurement device, comprising:
- a delta-sigma modulator configured to sample one of voltage or current in a power system and output a 1-bit delta-sigma signal, the voltage or current having a system frequency;
- and
- a frequency locked-loop including,
- a 1-bit rotate CORDIC that receives a phase ramp signal and the 1-bit delta-sigma signal and outputs an in-phase difference signal and a quadrature-phase difference signal, the difference signals each having a multi-bit word for each bit of the 1-bit delta-sigma signal,
- a phase error calculator configured to receive the difference signals and to output a phase error signal based upon the difference between a phase of the phase ramp signal and the phase of the system frequency contained within the 1-bit delta-sigma signal,
- a frequency register containing a frequency value,
- a phase accumulator configured to produce the phase ramp signal having a periodicity determined by the frequency value,
- wherein the frequency locked-loop is configured to adjust the frequency value based upon the phase error signal so as to lock the frequency value to the system frequency.
A frequency locked-loop for locking to a system frequency of a signal sampled by a delta-sigma modulator, wherein the delta-sigma modulator outputs a 1-bit delta-sigma bitstream, the frequency locked-loop comprising:
- a 1-bit rotate CORDIC that receives a phase ramp signal and the 1-bit delta-sigma signal and outputs an in-phase difference signal and a quadrature-phase difference signal, the difference signals each having a multi-bit word for each bit of the 1-bit delta-sigma signal, the phase ramp signal being derived from a frequency value maintained by the frequency locked-loop;
- a phase error calculator configured to receive the difference signals and to output a phase error signal based upon the difference between a phase of the phase ramp signal and the phase of the system frequency contained within the 1-bit delta-sigma signal;
- and
- a phase accumulator configured to produce the phase ramp signal having a periodicity determined by the frequency value,
- wherein the frequency locked-loop is configured to adjust the frequency value based upon the phase error signal so as to lock the frequency value to the system frequency.
Dependencies are inferred from the claim text.