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US 9,156,673 B2Granted
Packaging to reduce stress on microelectromechanical systems
AssigneeFairchild Semiconductor Corporation
InventorsJanusz Bryzek, John Gardner Bloomsburgh, Cenk Acar
Life of this patent
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Abstract
One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.
Claims9
An apparatus, comprising:
- a via wafer including a main portion and an elongate arm having a first portion extending away from the main portion of the via wafer and a second portion extending about the main portion of the via wafer and separate from the main portion of the via wafer by a gap;
- and
- a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the via wafer;
- an application specific integrated circuit (ASIC) having a first surface coupled to the elongate arm of the via wafer using a first electrical interconnect and a second surface opposite to the first surface, the second surface having a second electrical interconnect centrally located on the second surface to couple the ASIC to a substrate,
- wherein the elongate arm and the location of the second electrical interconnect are configured to protect the microelectromechanical layer from deformation or stress.
2 more elements
Dependencies are inferred from the claim text.