Semiconductor memory device having adjustable refresh period, memory system comprising same, and method of operating same
AssigneeSamsung Electronics Co., Ltd.
InventorUk-Song Kang
Life of this patent
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Abstract
A semiconductor memory device includes a cell array including a plurality of cell regions, a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address, and a refresh address generator configured to generate the counting address and a modified address in response to a control signal, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells.
Claims18
A semiconductor memory device connected to a memory controller, the semiconductor memory device comprising:
- a cell array comprising a plurality of cell regions;
- a row decoder configured to drive rows corresponding to cell regions in which a refresh operation is to be performed, based on a counting address;
- and
- a refresh address generator configured to generate the counting address and a modified address as a refresh address in response to a control signal provided from the memory controller, wherein the modified address is generated by inverting at least one bit of the counting address, and wherein the semiconductor memory device performs concurrent refresh operations on a first cell region corresponding to the counting address and a second cell region corresponding to the modified address where the second cell region is determined to have weak cells,
- wherein the refresh address indicates that a refresh operation is to be performed on only the first cell region where the control signal is in a first logic state, and the refresh address indicates that a refresh operation is to be performed on both the first and second cell regions where the control signal is in a second logic state.
A memory system comprising a memory controller configured to control a refresh operation of a cell array in a semiconductor memory device, wherein the memory controller comprises:
- a weak address storing unit storing addresses of weak cell regions of the cell array;
- an address counter configured to generate a reference address indicating a cell region to be refreshed;
- and
- a comparator configured to compare a modified address derived from the reference address with the addresses of the weak cell regions and to output a matching signal according to a result of comparison,
- wherein the semiconductor memory device comprises
- the cell array,
- a row decoder configured to select a refresh row based on a received address,
- a refresh counter configured to generate a counting address designating one cell region on which a refresh operation is to be performed, and
- an address converter configured to invert at least one bit of the counting address in response to the matching signal output by the memory controller and to generate a refresh address for refreshing at least two cell regions together, wherein the at least two cell regions comprise a first cell region corresponding to the counting address and a second cell region corresponding to the modified address.
A method of operating a semiconductor memory device, the semiconductor memory device connected to a memory controller, the method comprising:
- generating a refresh address corresponding to a first cell region to be refreshed;
- generating a modified address in the semiconductor memory device by inverting at least one bit of the refresh address responsive to a control signal provided by the memory controller, the modified address corresponding to a second cell region different from the first cell region;
- determining whether the second cell region comprises weak cells;
- and
- upon determining that the second cell region comprises weak cells, performing concurrent refresh operations on the first and second cell regions.
Dependencies are inferred from the claim text.