Symmetric is linear equalization circuit with increased gain

A circuit for continuous time linear equalization of analog signals and analog computation, comprising:

• a first amplification element and a second amplification element with matched characteristics in a differential configuration, each amplification element having a first input and a second input,
• a third amplification element and a fourth amplification element with matched characteristics in a differential configuration, each amplification element having a first input and a second input,
• a first load impedance shared by the first amplification element and third amplification element, and a second load impedance shared by the second amplification element and fourth amplification element,
• a first, second, third, and fourth signal input, each directly connected to a first input of the corresponding first, second, third, and fourth amplification elements, respectively, and
• a frequency-dependent connection of the first, second, third, and fourth signal inputs to the second input of the fourth, third, second, and first amplification elements, respectively.

A circuit comprising:

• a first, second, third, and fourth transistor, each of the transistors having a drain, a gate, and a source, wherein the first and second transistors are arranged in a first differential amplifier pair, and the third and fourth transistors are arranged in a second differential amplifier pair;
• a capacitive coupling between the gate of the first, second, third, and fourth transistor to the source of the second, first, fourth, and third transistor, respectively;
• a first output node coupled to the drain of the first transistor and to the drain of the third transistor;
• and
• a second output node coupled to the drain of the second transistor and to the drain of the fourth transistor.

A circuit comprising:

• a first, second, third, and fourth transistor, each of the transistors having a drain, a gate, and a source, wherein the first and second transistors are arranged in a first differential amplifier pair, and the third and fourth transistors are arranged in a second differential amplifier pair;
• a capacitive coupling between the gate of the first, second, third, and fourth transistor to the source of the fourth, third, second, and first transistor, respectively;
• a first output node coupled to the drain of the first transistor and to the drain of the third transistor;
• and
• a second output node coupled to the drain of the second transistor and to the drain of the fourth transistor.

An analog computation circuit comprising:

• a plurality of amplification elements arranged in a plurality of differential pairs, each differential pair including a first and second amplification element, and each of the amplification elements having an inverting input and a non-inverting input;
• a first and a second differential summing output node, an output of each of the first amplification elements being connected to the first summing output node, and an output of each of the second amplification elements being connected to the second summing output node;
• a first plurality of gain-enhancing capacitive couplings, each of the first plurality of couplings connecting the inverting input of one of the first amplification elements with the non-inverting input of one of the second amplification elements;
• and
• a second plurality of gain-enhancing capacitive couplings, each of the second plurality of couplings connecting the inverting input of one of the second amplification elements with the non-inverting input of one of the first amplification elements.