On-chip power-combining for high-power schottky diode based frequency multipliers

A method for fabricating an integrated circuit or chip including a Monolithic Microwave Integrated Circuit (MMIC) on-chip power-combined frequency multiplier device, comprising:

• fabricating an integrated circuit comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and fabricating each of the multiplying structures includes:
• defining two or more Schottky diodes, wherein:
• the defining of each of the Schottky diodes includes defining a Schottky diode ohmic contact and mesa on a substrate, and
• the Schotty diodes are used as nonlinear semiconductor devices to generate harmonics out of an input signal and produce a multiplied output signal;
• forming interconnect metal comprising one or more stripline based input matching networks and one or more stripline based output matching networks, and input and output antennas or E-probes, the one or more stripline based input matching networks electrically connecting an input antenna or an input E-probe to the two or more Schottky diodes in a balanced configuration, the one or more stripline based output matching networks for transmitting the multiplied output signal from the Schottky diodes to an output antenna or an output E-probe, the input antenna or input E-probe for receiving the input signal in the millimeter-wave, submillimeter-wave, or terahertz frequency range inputted on the chip, and the output antenna or the output E-probe for transmitting the multiplied output signal off the single chip into one or more output waveguides each comprising a transmission line;
• defining and depositing Schottky anodes using electron beam lithography;
• defining bridge metal that connects the Schottky diodes to the interconnect metal;
• passivating the integrated circuit;
• etching the substrate to form a membrane layer;
• depositing ground and DC bias airbridges for the Schottky diodes;
• attaching the chip comprising the interconnect metal and the Schottky diodes onto a carrier wafer;
• removing the substrate with a selective etch;
• releasing the chip from the carrier wafer;
• and
• assembling the chip into a plated silicon-wafer based housing or thin metal plates-based housing;
• wherein:
• two or more of the input antennas or input E-probes divided the input signal equally among the multiplying structure with the chip;
• two or more of the output antennas or output E-probes combine the output signals at the one or more output waveguides,
• power-combining of the output signals is performed directly on chip;
• and
• an improvement in power-handling capabilities and output power of a factor equal to a number of the multiplying structures included in the chip is achieved.

A method of fabricating a Monolithic Microwave Integrated Circuit (MMIC) on-chip power-combined frequency multiplier device, comprising:

• fabricating an integrated circuit comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and fabricating each of the multiplying structures includes:
• fabricating one input antenna or input E-probe for receiving an input signal in the millimeter-wave, submillimeter-wave, or terahertz frequency range inputted on the chip,
• fabricating one or more stripline based input matching networks electrically connecting the input antenna or the input E-probe to two or more Schottky diodes in a balanced configuration,
• fabricating the two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce a multiplied output signal,
• fabricating one or more stripline based output matching networks for transmitting the multiplied output signal from the Schottky diodes to an output antenna or an output E-probe, and
• fabricating the output antenna or the output E-probe for transmitting the multiplied output signal off the single chip an output waveguide transmission line comprising output waveguide matching networks;
• and
• micro-machining a plurality of silicon wafers or thin metal plates including input and output waveguide matching networks as well as a waveguide channel where the frequency multiplier chip or integrated circuit is placed, wherein the silicon wafers or thin metal plates are aligned, stacked, and fastened together using alignment pins, screw holes or any other alignment technique;
• wherein:
• two or more of the input antennas or input E-probes divided the input signal equally among the multiplying structure within the chip;
• two or more of the output antennas or output E-probes combine the output signals at the output waveguides transmission line,
• power-combining of the output signals is performed directly on chip;
• and
• an improvement in power-handling capabilities and output power of a factor equal to a number of the multiplying structures included in the chip is achieved.