Digital filter for reducing the sampling rate of an input signal
AssigneeMBDA Deutschland GmbH
InventorGerhard Sedlak
Life of this patent
Estimating the term…
Abstract
A digital filter for reducing a sampling rate for an input signal includes a parallelizing block for splitting the input signal into at least two parallel raw signals, an integration block for converting the parallel raw signals into an intermediate signal, and a differentiation block for generating an output signal by differentiating the intermediate signal. The integration block includes a logic block that is designed for generating two parallel sum signals from the parallel raw signals using summation operations, and a recursion block that is designed for generating the intermediate signal recursively from the parallel sum signals.
Claims18
A digital filter, the digital filter comprising:
- a parallelizing hardware block configured to split an input signal into at least two parallel raw signals ue;
- an integration hardware block configured to convert the parallel raw signals ue into an intermediate signal SR;
- a differentiation hardware block configured to generate an output signal by differentiating the intermediate signal SR;
- wherein the integration hardware block includes a logic block configured to generate two parallel sum signals S0 and S1 in accordance with
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- from the parallel raw signals ue using summation operations, wherein ue(i) is the parallel raw signals and E is the number of parallel raw signals, and
- wherein the integration hardware block includes a recursion block configured to generate the intermediate signal SR recursively from the parallel sum signals S0 and S1,
- wherein the digital filter is configured to reduce a sampling rate of the input signal.
A radar sensor for a missile, comprising:
- a radar receiver;
- an A/D converter configured to convert an analog signal from the radar receiver to a digital signal;
- and
- a digital signal processor that includes a digital filter configured to reduce a sampling rate of an input signal, the digital filter including
- a parallelizing hardware block configured to split the input signal into at least two parallel raw signals ue;
- an integration hardware block configured to convert the parallel raw signals ue into an intermediate signal SR;
- a differentiation hardware block configured to generate an output signal by differentiating the intermediate signal SR;
- wherein the integration hardware block includes a logic block configured to generate two parallel sum signals S0 and S1 in accordance with
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- from the parallel raw signals ue using summation operations, wherein ue(i) is the parallel raw signals and E is the number of parallel raw signals, and
- wherein the integration hardware block includes a recursion block configured to generate the intermediate signal SR recursively from the parallel sum signals S0 and S1.
A method for operating a digital filter, the method comprising the steps:
- splitting, by a parallelizing hardware block, an input signal into at least two parallel raw signals ue;
- adding, by an integration hardware block, the parallel raw signals ue to two parallel sum signals S0 and S1 in accordance with
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- wherein ue(i) is the parallel raw signals and E is the number of parallel raw signals;
- recursively generating, by the integration hardware block, an intermediate signal SR from the parallel sum signals S0 and S1;
- and
- generating, by a differentiation hardware block, an output signal y by differentiating the intermediate signal SR,
- wherein the method reduces a sampling rate for the input signal.
Dependencies are inferred from the claim text.