# US 9,124,279 B2 · Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,124,279 B2
- Document ID: US9124279B2
- Status: Granted
- Kind: B2
- Application number: 13/602,216
- Filed: 2012-09-03
- Published: 2014-03-06
- Granted: 2015-09-01
- Earliest claimed: 2012-09-03
- Assignees: Tensorcom, Inc.
- Applicants: Dai Dai
- Inventors: Dai Dai
- Web page: https://patentgrep.com/patent/US9124279B2

## CPC

- H03K 5/2481: {with at least one differential stage}
- H03H 11/481: {Simulating capacitances}
- H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed}
- H03M 1/0845: {of power supply variations, e.g. ripple}
- H03M 1/183: {the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter}
- H03M 1/0836: {of phase error, e.g. jitter}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

## Claims

### Claim 1

A negative-capacitance apparatus comprising:
a first node coupled to a drain of a first transistor and a gate of a second transistor;
a second node coupled to a drain of said second transistor and a gate of said first transistor;
a capacitor coupled between a source of said first transistor and a source of said second transistor;
a first current mirror coupled between a supply voltage and said source of said first transistor; and
a second current mirror coupled between said supply voltage and said source of said second transistor;
a first amplifier that generates a differential signal coupled to said first and second nodes; and
a plurality of amplifiers that are driven by said differential signal coupled to said first and second nodes.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein
said first amplifier is a programmable gain amplifier.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein
each of said plurality of amplifiers comprises a pre-amplifier stage of a comparator.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein
said pre-amplifier stage of said comparator is a clock-less pre-amplifier.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein
each said pre-amplifier stage is abutted to one another such that an active transistor of a first differential stage in a first pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second pre-amplifier stage.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein
a coupling is formed between said first amplifier and said plurality of amplifiers.

### Claim 7

A method of increasing a transfer bandwidth of a differential signal comprising the steps of:
amplifying a differential input signal to provide said differential signal driving a differential capacitive load between a first node and a second node;
coupling said first node to a drain of a first transistor and a gate of a second transistor;
coupling said second node to a drain of said second transistor and a gate of said first transistor;
coupling a capacitor between a source of said first transistor and a source of said second transistor;
coupling a first current mirror between a supply voltage and said source of said first transistor;
coupling a second current mirror between said supply voltage and said source of said second transistor; and
causing said differential capacitive load to be driven in a shorter time period, thereby increasing said transfer bandwidth of said differential signal, wherein
a first amplifier generates said differential input signal and a plurality of amplifiers receive said differential input signal.

### Claim 8 (depends on 7)

The method of claim 7, wherein
said differential capacitive load comprises a differential capacitance of a differential interconnect, a differential input capacitance of said plurality of amplifiers and a differential drain capacitance of said first amplifier.

### Claim 9 (depends on 7)

The method of claim 7, wherein
said first amplifier is a programmable gain amplifier.

### Claim 10 (depends on 7)

The method of claim 7, wherein
each of said plurality of amplifiers is a clock-less pre-amplifier stage of a comparator.

### Claim 11 (depends on 10)

The method of claim 10, further comprising the steps of:
abutting a plurality of clock-less pre-amplifier stages to one another such that an active transistor of a first differential stage in a first clock-less pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second clock-less pre-amplifier stage.

### Claim 12

An apparatus comprising:
a first amplifier coupled to a first node and a second node;
a differential capacitive load coupled to said first node and said second node;
said differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit;
a current source coupled to a source of each transistor;
a capacitor coupled between said sources of said transistors; and
a plurality of amplifiers coupled to said first and said second node.

### Claim 13 (depends on 12)

The apparatus of claim 12, further comprising:
a differential signal of said first amplifier drives said first and said second nodes.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein
each of said plurality of amplifiers is a clock-less pre-amplifier stage of a comparator.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein
each said clock-less pre-amplifier stage is abutted to one another such that an active transistor of a first differential stage in a first clock-less pre-amplifier stage behaves as a dummy transistor for an adjacent differential stage in a second clock-less pre-amplifier stage.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein
said first amplifier is a programmable gain amplifier.