Air gap isolation in non-volatile memory using sacrificial films

A method of fabricating non-volatile storage, comprising:

• forming a plurality of layer stack columns over a substrate and a plurality of isolation trenches in the substrate separating adjacent active areas, each active area of the substrate underlying one layer stack column, each layer stack column having a strip of charge storage material separated from the substrate by a strip of dielectric material;
• filling each isolation trench and a space between adjacent layer stack columns with a sacrificial film using flowable chemical vapor deposition;
• oxidizing the sacrificial film to harden an upper region of the sacrificial film while increasing an etch rate of a lower region of the sacrificial film;
• etching back the sacrificial film;
• forming an intermediate dielectric layer and a control gate layer after etching back the sacrificial film;
• and
• etching orthogonally to the layer stack columns to form a plurality of layer stack rows, each layer stack row including a control gate etched from the control gate layer that extends over a row of charge storage regions from the strips of charge storage material;
• wherein etching orthogonally to the layer stack columns includes removing at least a portion of the lower region of the sacrificial film while maintaining at least a portion of the upper region of the sacrificial film to form a bit line air gap at least partially in each isolation trench, the bit line air gap having an upper endpoint underlying the layer stack rows that is defined by a lower surface of the upper region of the sacrificial film.

A method of fabricating non-volatile storage, comprising:

• etching a layer stack into a plurality of layer stack columns over a substrate, each layer stack column including a strip of charge storage material;
• etching the substrate into a plurality of isolation trenches separated by adjacent active areas, each active area of the substrate underlying one layer stack column;
• forming a first sacrificial film at least partially in the plurality of isolation trenches and a second sacrificial film over the first sacrificial film at least partially between adjacent layer stack columns, the first sacrificial film having a first etch rate and the second sacrificial film having a second etch rate that is lower than the first etch rate;
• recessing the second sacrificial film below an upper surface of the strips of charge storage material;
• forming an intermediate dielectric layer and a control gate layer after recessing the second sacrificial film;
• and
• etching to form a plurality of layer stack rows including first and second sidewalls, each layer stack row including a control gate that extends over a row of charge storage regions formed from the strips of charge storage material;
• forming a liner along the first and second sidewalls of each layer stack row;
• and
• removing at least a portion of the first sacrificial film after forming the liner to form a bit line air gap at least partially in each isolation trench.