Liquid crystal display

A liquid crystal display comprising:

• a display area comprising:
• a plurality of pixel electrodes arranged substantially in a matrix form including a plurality of pixel rows and a plurality of pixel columns;
• a plurality of data lines extending substantially in a pixel column direction, wherein each data line is disposed between two adjacent pixel columns;
• and
• a plurality of gate lines extending substantially in a pixel row direction, wherein the gate lines are in two-to-one correspondence with the pixel rows,
• wherein a first data line of the data lines is disposed between a first pixel electrode and a second pixel electrode of the pixel electrodes,
• wherein the first pixel electrode and the second pixel electrode are disposed in a same pixel row between a first gate line and a second gate line of the gate lines, which are adjacent to each other,
• wherein the first pixel electrode is connected to a first thin film transistor comprising a first source electrode connected to the first data line, a first drain electrode opposite to the first source electrode, and a first gate electrode, and
• wherein the second pixel electrode is connected to a second thin film transistor comprising a second source electrode connected to the first data line, a second drain electrode opposite to the second source electrode, and a second gate electrode;
• and
• a peripheral area comprising:
• a first parasitic capacitor capacity measuring unit comprising a plurality of first gate capacity units and a plurality of first data capacity units;
• and
• a second parasitic capacitor capacity measuring unit comprising a plurality of second gate capacity units and a plurality of second data capacity units,
• wherein a relative arrangement between the first gate capacity units and the first data capacity units is substantially the same as a relative arrangement between the first gate electrode and the first drain electrode;
• and
• wherein a relative arrangement between the second gate capacity units and the second data capacity units is substantially the same as a relative arrangement between the second gate electrode and the second drain electrode.