Row hammer refresh command
AssigneeIntel Corporation
InventorsKuljit Bains, John Halbert, Christopher Mozak, Theodore Schoenborn, Zvika Greenfield
Life of this patent
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Abstract
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
Claims15
A system comprising:
- a synchronous dynamic random access memory (SDRAM) device, the SDRAM device including:
- a memory array to include one or more rows of memory cells;
- a mode register to hold at least one mode register bit, the value of the at least one mode register bit to determine whether a targeted row refresh mode is enabled;
- and
- targeted row refresh logic coupled with the memory array, the targeted row refresh logic capable of refreshing selected rows responsive, at least in part, to a targeted row refresh command, the refreshing selected rows performed as a targeted row refresh having a refresh time (tRF) that is shorter than a refresh cycle time (tRFC) for the row;
- and
- a memory controller coupled with the SDRAM device, the memory controller including detection logic to detect a targeted row refresh condition;
- and
- command and control logic capable to issue a command to set the at least one mode register bit to transition the SDRAM device to the targeted row refresh mode, subsequent to detection of the targeted row refresh condition.
A synchronous dynamic random access memory (SDRAM) device, the SDRAM device comprising:
- a memory army to include one or more rows of memory cells;
- a mode register to hold at least one mode register bit, the value of the at least one mode register bit to determine whether a targeted row refresh mode is enabled;
- and
- targeted row refresh logic coupled with the memory array, the targeted row refresh logic capable to refresh selected rows responsive, at least in part, to a targeted row refresh command, the refresh of selected rows performed as a targeted row refresh having a refresh time (tRF) that is shorted than a refresh cycle time (tRFC) for the row.
A memory controller comprising:
- a double data rate (DDR) interface to couple the memory controller to a DDR memory channel;
- detection logic to detect a targeted row refresh condition;
- and
- command and control logic capable to issue a command to transition a synchronous dynamic random access memory (SDRAM) device to a targeted row refresh mode, subsequent to detection of the targeted row refresh condition, to enable the SDRAM to perform a targeted row refresh having a refresh time (tRF) that is shorter than a refresh cycle time (tRFC) for the row.
Dependencies are inferred from the claim text.